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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Electronic and thermal properties of the phase-change memory material, Ge 2 Sb 2 Te 5 , and results from spatially resolved transport calculations

Here, we report new insights into the electronic, structural, and transport (heat and charge) properties of the phase-change memory material amorphous Ge 2 Sb 2 Te 5 . Using realistic structural models of Konstantinou et al., (2019), we analyze the topology, electronic states, and lattice dynamics with density functional methods, including hybrid-functional calculations and machine-learned interatomic potentials. The Kohn–Sham orbitals near the Fermi level display a strong electron–phonon coupling, and exhibit large energy fluctuations at room temperature. The conduction tail states exhibit larger phonon-induced fluctuations than the valence tail states. To resolve transport at the atomic scale, we employ space-projected electronic conductivity and site-projected thermal conductivity methods. Local analysis of heat transport highlights the role of filamentary networks dominated by Te, with Sb and Ge making progressively smaller contributions.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

Recent advancements in chiral spintronics: from molecular-level insights to device applications. A prospect based on the interplay between physical and chemical properties of chiral systems

This review discusses recent advancements in chiral-based spin-electronic devices achieved using suitable combinations of organic, inorganic and hybrid materials. The focus is on how chirality can be effectively used to control spin in practical applications, particularly in spintronic sensors and consumer devices. Interestingly, the underlying mechanism for this control is the chiral-induced spin selectivity (CISS) effect, which links the structural chirality of a material to its spin-selective electronic transport properties. The CISS effect arises from the observation that charge transmission in chiral systems is spin selective. Experimental evidence suggests a relationship between electron spin and the structural handedness of the material. In conclusion, this unique structure-transport relationship can be exploited to design a wide range of spintronics devices, including memory, transistors, logic gates and molecular q-bits.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

Evidence of Cooperative Effects for the Fe(phen) 2 (NCS) 2 Spin Crossover Molecular Complex in Polyaniline Plus Iron Magnetite

The spin crossover complex Fe(phen) 2 (NCS) 2 and its composite, Fe(phen) 2 (NCS) 2 , combined with the conducting polymer polyaniline (PANI) plus varying concentrations of iron magnetite (Fe 3 O 4 ) nanoparticles were studied. A cooperative effect is evident from the hysteresis width in the plot of magnetic susceptibility multiplied by temperature versus temperature (χ m T versus T) for Fe(phen) 2 (NCS) 2 with PANI plus varying concentrations of Fe 3 O 4 nanoparticles. The hysteresis width in the composites vary no more than 2 K with respect to the pristine Fe(phen) 2 (NCS) 2 spin crossover crystallites despite the fact that there exists a high degree of miscibility of the Fe(phen) 2 (NCS) 2 spin crossover complex with the PANI. The Fe 3 O 4 nanoparticles in the Fe(phen) 2 (NCS) 2 plus PANI composite tend to agglomerate at higher concentrations regardless of the spin state of Fe(phen) 2 (NCS) 2 . Of note is that the Fe 3 O 4 nanoparticles are shown to be antiferromagnetically coupled with the Fe(phen) 2 (NCS) 2 when Fe(phen) 2 (NCS) 2 is in the high spin state.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗
NASA NTRS1991

Stacked-Gate FET's For Analog Memory Elements

Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

Thakoor, Anilkumar P.↗
NASA NTRS1993

An ASIC memory buffer controller for a high speed disk system

The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

Hodson, Robert F.↗
NASA NTRS1997

Robotic Assisted Microsurgery - RAMS FY'97

JPL and Microdexterity Systems collaborated to develop new surgical capabilities. They developed a Robot Assisted Microsurgery (RAM) tool for surgeons to use for operating on the eye, ear, brain, and blood vessels with unprecedented dexterity. A surgeon can hold the surgical instrument with motions of 6 degrees of freedom with an accuracy of 25 microns in a 70 cu cm workspace. In 1996 a demonstration was performed to remove a microscopic particle from a simulated eyeball. In 1997, tests were performed at UCLA to compare telerobotics with mechanical operations. In 5 out of 7 tests, the RAM tool performed with a significant improvement of preciseness over mechanical operation. New design features include: (1) amplified forced feedback; (2) simultaneous slave robot instrumentation; (3) index control switch on master handle; and (4) tool control switches. Upgrades include: (1) increase in computational power; and (2) installation of hard disk memory storage device for independent operation and independent operation of forceps. In 1997 a final demonstration was performed using 2 telerobotics simultaneously in a microsurgery suture procedure to close a slit in a thin sheet of latex rubber which extended the capabilities of microsurgery procedures. After completing trials and demonstrations for the FDA the potential benefits for thousands of operations will be exposed.

Source record↗
NASA NTRS2008

Carbon Nanotube Switches for Communication and Memory Applications

Lateral CNT Switches: a) dc CNT switches were demonstrated to operate at low voltages, low powers and high speeds. b) RF simulations of switch in series configuration with metallized tube yielded good RF performance 1) Isolation simulated to be approx. 20 dB at 100 GHz. 2) Insertion loss simulated to be < 0.5 dB at 100 GHz. Vertical CNT Switches: a) Thermal CVD was used to mechanically constrain tubes in nanopockets; tubes not self-supporting. b) Demonstrated growth of vertically aligned arrays and single-few MWNTs using dc PECVD with Ni catalyst using optical lithography.

memory devices↗
NASA NTRS2019

NASA Electronic Parts and Packaging (NEPP) Program Status and Technology Investments Overview

The presentation provides an updated, high-level overview of the NEPP Program. The latest organizational chart is presented that shows the names of the Program and Assistant Program Managers. Additionally, the recent work that is on-going with the updating of several NASA NPDs, NPRs and technical standards is reviewed. Internal and external organizational interfaces are described. Finally, the current technology focus areas are described. These areas include passives, wide-band gap power devices, processor units (CPUs and GPUs), 2.5D and 3D device architectures, memories, and data analytics.

NEPAG↗
NASA NTRS1985

Bubble memory module for spacecraft application

Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

Hayes, P. J.↗
NASA NTRS1978

Test and evaluation of bubble memories

A description is presented of a test program which has shown that well-constructed bubble memories can operate reliably over long periods of time and at low error rates. Even the relatively high error rate of one memory during burn-in can be considered acceptable if compared with tape recorder standards. No wear-out mechanism or aging could be detected. Bubble memories are now considered suitable for long-duration space missions and certainly are suitable for many military and commercial applications. It must be recognized, however, that bubble memories are complex devices and not yet fully understood. While the particular memory tested may never find practical applications, it nevertheless has provided insight into performance characteristics considered typical of bubble memories.

Bahm, E.↗
NASA NTRS2007

Analog Nonvolatile Computer Memory Circuits

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

MacLeod, Todd↗
NASA NTRS2008

Disturb testing in flash memories

Non-volatile memory technology as defined by NAND architecture flash memory continues to lead the process scaling and device shrinking efforts of the entire integrated circuit industry. 45- nm technology nodes are now producing commercial 32Gb devices. These latest 32Gb devices are pioneering new charge trapping memory cell technologies using metal gates and high-k dielectric materials. These cells are called TANOS and consist of tantalum-nitride, aluminum oxide (high k material), nitride, oxide, and silicon. Such high-density memories continue to revolutionize commercial electronics in terms of new high-speed data architectures and significant reductions in overall power and weight consumption. In stark contrast, nearly all science-based interplanetary and earth-orbiting NASA spacecraft are still designing in and around mid-1980s-level non-volatile technology with 1Mb Electrically Erasable Read-Only Memory (EEPROM) devices. NASA has typically shunned the use of modern flash devices because of radiation and reliability concerns due to the commercial-offthe– shelf (COTS) nature of the NAND flash technology. Given the significant potential increases in overall system capability these modern flash devices could bring to NASA missions, it is important to continue to investigate these devices. This report will investigate certain portions of the reliability performance of NAND flash devices, specifically the disturb properties. Understanding the possible limitations such new non-volatile memory technology presents to NASA is the goal of this report.

Freie, Michael↗
NASA NTRS1994

Performance issues for iterative solvers in device simulation

Due to memory limitations, iterative methods have become the method of choice for large scale semiconductor device simulation. However, it is well known that these methods still suffer from reliability problems. The linear systems which appear in numerical simulation of semiconductor devices are notoriously ill-conditioned. In order to produce robust algorithms for practical problems, careful attention must be given to many implementation issues. This paper concentrates on strategies for developing robust preconditioners. In addition, effective data structures and convergence check issues are also discussed. These algorithms are compared with a standard direct sparse matrix solver on a variety of problems.

Fan, Qing↗
NASA NTRS2010

Electrical Switching of Perovskite Thin-Film Resistors

Electronic devices that exploit electrical switching of physical properties of thin films of perovskite materials (especially colossal magnetoresistive materials) have been invented. Unlike some related prior devices, these devices function at room temperature and do not depend on externally applied magnetic fields. Devices of this type can be designed to function as sensors (exhibiting varying electrical resistance in response to varying temperature, magnetic field, electric field, and/or mechanical pressure) and as elements of electronic memories. The underlying principle is that the application of one or more short electrical pulse(s) can induce a reversible, irreversible, or partly reversible change in the electrical, thermal, mechanical, and magnetic properties of a thin perovskite film. The energy in the pulse must be large enough to induce the desired change but not so large as to destroy the film. Depending on the requirements of a specific application, the pulse(s) can have any of a large variety of waveforms (e.g., square, triangular, or sine) and be of positive, negative, or alternating polarity. In some applications, it could be necessary to use multiple pulses to induce successive incremental physical changes. In one class of applications, electrical pulses of suitable shapes, sizes, and polarities are applied to vary the detection sensitivities of sensors. Another class of applications arises in electronic circuits in which certain resistance values are required to be variable: Incorporating the affected resistors into devices of the present type makes it possible to control their resistances electrically over wide ranges, and the lifetimes of electrically variable resistors exceed those of conventional mechanically variable resistors. Another and potentially the most important class of applications is that of resistance-based nonvolatile-memory devices, such as a resistance random access memory (RRAM) described in the immediately following article, Electrically Variable Resistive Memory Devices (MFS-32511-1).

Liu, Shangqing↗
NASA NTRS1996

Report on Alternative Devices to Pyrotechnics on Spacecraft

Pyrotechnics accomplish many functions on today's spacecraft, possessing minimum volume/weight, providing instantaneous operation on demand, and requiring little input energy. However, functional shock, safety, and overall system cost issues, combined with emergence and availability of new technologies question their continued use on space missions. Upon request from the National Aeronautics and Space Administration's (NASA) Program Management Council (PMC), Langley Research Center (LaRC) conducted a survey to identify and evaluate state-of-the-art non-explosively actuated (NEA) alternatives to pyrotechnics, identify NEA devices planned for NASA use, and investigate potential interagency cooperative efforts. In this study, over 135 organizations were contacted, including NASA field centers, Department of Defense (DOD) and other government laboratories, universities, and American and European industrial sources resulting in further detailed discussions with over half, and 18 face-to-face briefings. Unlike their single use pyrotechnic predecessors, NEA mechanisms are typically reusable or refurbishable, allowing flight of actual tested units. NEAs surveyed include spool-based devices, thermal knife, Fast Acting Shockless Separation Nut (FASSN), paraffin actuators, and shape memory alloy (SMA) devices (e.g., Frangibolt). The electro-mechanical spool, paraffin actuator and thermal knife are mature, flight proven technologies, while SMA devices have a limited flight history. There is a relationship between shock, input energy requirements, and mechanism functioning rate. Some devices (e.g., Frangibolt and spool based mechanisms) produce significant levels of functional shock. Paraffin, thermal knife, and SMA devices can provide gentle, shock-free release but cannot perform critically timed, simultaneous functions. The FASSN flywheel-nut release device possesses significant potential for reducing functional shock while activating nearly instantaneously. Specific study recommendations include: (1) development of NEA standards, specifically in areas of material characterization, functioning rates, and test methods; (2) a systems level approach to assure successful NEA technology application; and (3) further investigations into user needs, along with industry/government system-level real spacecraft cost benefit trade studies to determine NEA application foci and performance requirements. Additional survey observations reveal an industry and government desire to establish partnerships to investigate remaining unknowns and formulate NEA standards, specifically those driven by SMAs. Finally, there is increased interest and need to investigate alternative devices for such functions as stage/shroud separation and high pressure valving. This paper summarizes results of the NASA-LaRC survey of pyrotechnic alternatives. State of-the-art devices with their associated weight and cost savings are presented. Additionally, a comparison of functional shock characteristics of several devices are shown, and potentially related technology developments are highlighted.

Lucy, M. H.↗
NASA NTRS1979

Aerospace Ground Equipment for model 4080 sequence programmer. A standard computer terminal is adapted to provide convenient operator to device interface

The Aerospace Ground Equipment (AGE) provides an interface between a human operator and a complete spaceborne sequence timing device with a memory storage program. The AGE provides a means for composing, editing, syntax checking, and storing timing device programs. The AGE is implemented with a standard Hewlett-Packard 2649A terminal system and a minimum of special hardware. The terminal's dual tape interface is used to store timing device programs and to read in special AGE operating system software. To compose a new program for the timing device the keyboard is used to fill in a form displayed on the screen.

Nissley, L. E.↗