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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
DOE OSTI2019

Programmable Electrofluidics for Ionic Liquid Based Neuromorphic Platform

Due to the limit in computing power arising from the Von Neumann bottleneck, computational devices are being developed that mimic neuro-biological processing in the brain by correlating the device characteristics with the synaptic weight of neurons. This platform combines ionic liquid gating and electrowetting for programmable placement/connectivity of the ionic liquid. In this platform, both short-term potentiation (STP) and long-term potentiation (LTP) are realized via electrostatic and electrochemical doping of the amorphous indium gallium zinc oxide (aIGZO), respectively, and pulsed bias measurements are demonstrated for lower power considerations. While compatible with resistive elements, we demonstrate a platform based on transitive amorphous indium gallium zinc oxide (aIGZO) pixel elements. Using a lithium based ionic liquid, we demonstrate both potentiation (decrease in device resistance) and depression (increase in device resistance), and propose a 2D platform array that would enable a much higher pixel count via Active Matrix electrowetting.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Optimized Viewing Techniques to Minimize Radiation Damage From X-ray Imaging Systems

X-ray inspection of ball grid arrays (BGAs) is typically performed at one or more viewing angles to examine adhesion sites for errors such as voids, joint cracking, or head-in-pillow. During this inspection process, the cir cuit board assembly is subject to ionizing radiation exposure, which can cause trapped charge within oxide layers of semiconductor devices. Some x-ray machines allow for programmable inspection routines, which could be used to optimize radiation exposure to semiconductor components. Using Monte Carlo methods, x-ray inspection of a BGA was simulated to determine a range of acceptable viewing angles. Dose rates to circuit board components were estimated at each inspection angle to determine the view resulting in optimized radiation exposure. Results showed that for each BGA, the maximum unobstructed viewing times without exceeding a 5 Gy dose limit to a single part ranged from 82 to 94 minutes. Using a radiation cost function method, optimized viewing across all components was found. Here, it was observed that for a consistent dose limit applied to silicon-based components, performing inspection with BGAs facing the x-ray source was optimal. A third method was applied, assigning individual dose limits based on empirical data from the NASA Goddard Space Flight Center radiation database. This method showed that optimized viewing maximizes the distance between the radiation source and highly sensitive components. It was also observed that cumulative effects from viewing two BGAs will influence viewing angles, causing the optimal view of one BGA to exist nearly 180° from the other.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Unconventional ferroelectricity in moiré heterostructures

Although all matter is composed of component particles, these particles can arrange themselves in various ways, giving rise to emergent phenomena that can be surprisingly rich and often cannot be understood by studying only the individual constituents. Discovering and understanding novel forms of emergence in quantum materials, especially in those where multiple degrees of freedom or energy scales are delicately balanced, is of great fundamental interest to condensed matter research. In this work, we report on the surprising observation of emergent ferroelectricity in graphene-based moiré heterostructures. Ferroelectric materials exhibit an electrically-switchable electric dipole, which is usually formed by spatial separation between the averaged centers of positive and negative charge within the unit cell. Based on this, it is difficult to imagine graphene, a material composed only of carbon atoms, exhibiting ferroelectricity. However, in this work, we indeed realize switchable ferroelectricity in Bernal-stacked bilayer graphene sandwiched between two hexagonal boron nitride (BN) layers. By introducing a moiré superlattice potential (via aligning bilayer graphene with the top and/or bottom BN crystals), we observe prominent and robust hysteretic behavior of the graphene resistance with an externally applied out-of-plane displacement field. Our systematic transport measurements reveal rich and striking response as a function of displacement field and electron filling, not previously observed in any 2D systems, and beyond the framework of conventional ferroelectrics. We further directly probe the ferroelectric polarization through a nonlocal monolayer graphene sensor. Our results suggest an unconventional, odd parity electronic ordering in the bilayer graphene/BN moiré system. This emergent moiré ferroelectricity may pave the way for ultrafast, programmable, and atomically thin carbon-based memory devices.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2018

An FPGA-Based Voltage Balancing Control for Multi-HV-IGBTs in Series Connection

The series connection of insulated gate bipolar transistors (IGBTs) allows operation at voltage levels higher than the rated voltage of one IGBT and has less power semiconductor costs compared to multilevel topologies. However, voltage unbalance during the switching transient is a challenge for series-connected device application. This paper presents an field-programmable gate array (FPGA)-based voltage balancing strategy for multiseries-connected high-voltage (HV)-IGBTs including an FPGA-based active voltage balancing control (AVBC) circuit integrated into the gate driver and the control for multiseries-connected IGBTs. As a result, the effectiveness of the control has been experimentally validated in a prototype using four 4.5 kV HV-IGBTs in series connection.

42 ENGINEERING↗
DOE OSTI2026

Supervisory Control and Data Acquisition for Electrochemical Separation Experimentation

The Python-based program is a laboratory automation tool designed to control and monitor electrochemical systems. The tool was developed for capacitive deionization (CDI) experiments, but it can be used for any system that requires controlled voltage or current segments and multi-parameter monitoring. The program integrates hardware components to run user-defined experimental parameters, providing operational control of a programmable power supply, peristaltic pump, and data acquisition devices. Currently, the program is structured with a workflow that includes an initialization (or pre-run) phase, a main loop, and a post-experiment stabilization (or post-run) phase. The initialization phase prepares and stabilizes the cell, ensuring that the electrodes and solution reach a baseline state before the experiment begins. The main loop consists of multiple voltage segments that repeat, controlling the experiment while recording key parameters such as time, voltage, current, pH, and conductivity. Finally, the post-experiment stabilization phase allows the system to stabilize after the experiment, returning the cell and solution to equilibrium conditions before ending the sequence. The program is designed with four variations, each tailored to different experimental needs. All variations include both the initialization and post-experiment stabilization stages, which run for a set amount of time, voltage, current, and flow rate before and after the main experiment block. The main loop runs for a set number of cycles, as defined by the user input, and each cycle is composed of 2 or 4 segments. The 4 program variations are described as follows: Program 1: The main program includes 2 segments. Each segment is defined to have a set duration, flow rate, voltage, and current. This program measures conductivity, flow rate, voltage, and current. Program 2: The main program expands Program 1 to include 4 segments. Each segment has a specified duration, flow rate, voltage, and current. Like Program 1, it measures conductivity, flow rate, voltage, and current. Program 3: The main program consists of 2 segments, each defined by time, flow rate, voltage, and current. In addition to conductivity, flow rate, voltage, and current, Program 3 collects pH and temperature data through a 4-channel data acquisition device. Program 4: This program independently controls two channels of a multi-channel power supply simultaneously. While conductivity can only be measured for one cell at a time, the dual-channel control makes it possible to operate two cells simultaneously under different voltage/current conditions. The main program includes 2 segments.For each program, all measurements are automatically logged and integrated into a single Excel output file. Data are displayed in numerical format and plotted, both in real time, to track system performance. A key feature of the program is its ability to synchronize all outputs so that every measurement shares a single timestamp, ensuring accurate alignment of voltage, current, pH, conductivity, and pH data.By combining hardware control, real-time monitoring, and unified data collection, this program significantly reduces manual workload and minimizes errors, making it a reliable platform for researchers, engineers, and laboratory technicians conducting CDI experiments, among other electrochemical tests.

Valentino, Lauren [Argonne National Laboratory (AN↗
NASA NTRS1986

Test and evaluation of a multifunction keyboard and a dedicated keyboard for control of a flight management computer

A flight management computer (FMC) control display unit (CDU) test was conducted to compare two types of input devices: a fixed legend (dedicated) keyboard and a programmable legend (multifunction) keyboard. The task used for comparison was operation of the flight management computer for the Boeing 737-300. The same tasks were performed by twelve pilots on the FMC control display unit configured with a programmable legend keyboard and with the currently used B737-300 dedicated keyboard. Flight simulator work activity levels and input task complexity were varied during each pilot session. Half of the points tested were previously familiar with the B737-300 dedicated keyboard CDU and half had no prior experience with it. The data collected included simulator flight parameters, keystroke time and sequences, and pilot questionnaire responses. A timeline analysis was also used for evaluation of the two keyboard concepts.

Crane, J. M.↗
NASA NTRS2010

Flexible Peripheral Component Interconnect Input/Output Card

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Bigelow, Kirk K.↗
NASA NTRS2016

Usable Translational Hand Controllers for NASA's Habitability Design Center

This summer I was given the opportunity to work at the Habitability Design Center (HDC). NASA Johnson Space Center's HDC is currently developing Cislunar and Mars spacecraft mockups. I contributed to this effort by designing from scratch low cost, functional translational hand controllers (THCs) that will be used in spacecraft mission simulation in low to medium fidelity exploration spacecraft mockups. This project fell under the category of mechatronics, a combination of mechanical, electrical, and computer engineering. Being an aerospace engineering student, I was out of my comfort zone. And that was a wonderful thing. The autonomy that my mentor, Dr. Robert Howard, allowed me gave me the opportunity to learn by trying, failing, and trying again. This project was not only a professional success for me, but a significant learning experience. I appreciated the freedom that I had to take the time to learn new things for myself rather than blindly follow instructions. I was the sole person working on this project, and was required to work independently to solve the many hardware and software challenges that the project entailed. I researched THCs that have been used on the ISS, the Space Shuttle, and the Orion MPVC and based my design off of these. I worked through many redesigns before finding an optimal configuration of the necessary mechanisms and electrical components for the THC. Once I had a functional hardware design, I dove into the challenge of getting an Arduino Uno, an extremely low cost and easily programmable microcontroller, to behave as a human interface device. The THCs I built needed to be able to integrate to a mission simulation designed by NASA's Graphics and Visualization Lab. This proved to be the most challenging aspect of the project. To accomplish this I learned how to change the firmware of the USB serial converter microcontroller. The process was very complicated as it involved multiple software programs and manual flashing of pins on the Arduino itself. When I successfully achieved the goal I wrote an instructions manual for the process so that the HDC will be able to do this easily in the future for any human interface device they may want to create. I also created a detailed CAD model of my THC design with construction instructions. My THC utilizes three ultrasonic sensors, one for each axis of motion. I wrote a code that stimulates these sensors continuously and feeds back values from each axis ranging from -%100 to %100 of the min/max position in relation to the neutral position of each axis. This was the data that the Graphics and Visualization Lab required to interface with their simulation. I truly enjoyed working in the HDC surrounded by passionate, proactive, and brilliantly creative people. I felt valued and respected as a part of their team. I was given the time and support of my mentor whenever I asked for it. Beyond my positive project experience, I was fortunate enough to be able to take advantage of many of the extra activities that JSC has to offer. I took Russian Phase One during my lunch break every day and can now read Russian and accomplish basic verbal communication. I was heavily involved with the co-tern music video, which led to numerous incredible experiences and friendships. I saw every facility, attended every lecture, and met everyone that I could. I had coffee with Lauri Hansen. I played on an intern volleyball team at the Gilruth. I traveled to Michoud, Stennis, NOLA, and Big Bend National Park. I had the time of my life and I fell in love with JSC. In the next month I will return to Maryland and start my senior year of my undergraduate degree. As I work through it I will remember that all of the studying I do, all of the concentration I give, and all of the sacrifices that I make for school are so that I can work at a place like JSC where I am proud and excited to go into work every day. This internship was an invaluable experience for me, both professionally and personally.

Westbrook, Kimberly↗
DOE OSTI2020

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

42 ENGINEERING↗
DOE OSTI2020

CCAMP: An Integrated Translation and Optimization Framework for OpenACC and OpenMP

Heterogeneous computing and exploration into specialized accelerators are inevitable in current and future supercomputers. Although this diversity of devices is promising for performance, the array of architectures presents programming challenges. High-level programming strategies have emerged to face these challenges, such as the OpenMP offloading model and OpenACC. The varying levels of support for these standards, however, within vendor-specific and open-source tools, as well as the lack of performance portability across devices, have prevented the standards from achieving their goals. To address these shortcomings, we present CCAMP, an OpenMP and OpenACC interoperable framework. CCAMP provides two primary facilities: language translation between the two standards and device-specific directive optimization within each standard. We show that by using the CCAMP framework, programmers can easily transplant non-portable code into new ecosystems for new architectures. Additionally, by using CCAMP device-specific directive optimizations, users can achieve optimized performance across architectures using a single source code.

Lambert, Jacob↗
NASA NTRS2011

S-Band POSIX Device Drivers for RTEMS

This is a set of POSIX device driver level abstractions in the RTEMS RTOS (Real-Time Executive for Multiprocessor Systems real-time operating system) to SBand radio hardware devices that have been instantiated in an FPGA (field-programmable gate array). These include A/D (analog-to-digital) sample capture, D/A (digital-to-analog) sample playback, PLL (phase-locked-loop) tuning, and PWM (pulse-width-modulation)-controlled gain. This software interfaces to Sband radio hardware in an attached Xilinx Virtex-2 FPGA. It uses plug-and-play device discovery to map memory to device IDs. Instead of interacting with hardware devices directly, using direct-memory mapped access at the application level, this driver provides an application programming interface (API) offering that easily uses standard POSIX function calls. This simplifies application programming, enables portability, and offers an additional level of protection to the hardware. There are three separate device drivers included in this package: sband_device (ADC capture and DAC playback), pll_device (RF front end PLL tuning), and pwm_device (RF front end AGC control).

Lux, James P.↗
DOE OSTI2023

An Interface–Type Memristive Device for Artificial Synapse and Neuromorphic Computing

Interface-type (IT) metal/oxide Schottky memristive devices have attracted considerable attention over filament-type (FT) devices for neuromorphic computing because of their uniform, filament-free, and analog resistive switching (RS) characteristics. The most recent IT devices are based on oxygen ions and vacancies movement to alter interfacial Schottky barrier parameters and thereby control RS properties. However, the reliability and stability of these devices have been significantly affected by the undesired diffusion of ionic species. Herein, a reliable interface-dominated memristive device is demonstrated using a simple Au/Nb-doped SrTiO 3 (Nb:STO) Schottky structure. The Au/Nb:STO Schottky barrier modulation by charge trapping and detrapping is responsible for the analog resistive switching characteristics. Because of its interface-controlled RS, the proposed device shows low device-to-device, cell-to-cell, and cycle-to-cycle variability while maintaining high repeatability and stability during endurance and retention tests. Furthermore, the Au/Nb:STO IT memristive device exhibits versatile synaptic functions with an excellent uniformity, programmability, and reliability. A simulated artificial neural network with Au/Nb:STO synapses achieves a high recognition accuracy of 94.72% for large digit recognition from MNIST database. These results suggest that IT resistive switching can be potentially used for artificial synapses to build next-generation neuromorphic computing.

36 MATERIALS SCIENCE↗
DOE OSTI2020

A broad-host-range event detector: expanding and quantifying performance between Escherichia coli and Pseudomonas species

Modern microbial biodesign relies on the principle that well-characterized genetic parts can be reused and reconfigured for different functions. However, this paradigm has only been successful in a limited set of hosts, mostly comprised from common lab strains of Escherichia coli . It is clear that new applications such as chemical sensing and event logging in complex environments will benefit from new host chassis. This study quantitatively compared how the same chemical event logger performed across four strains and three different microbial species. An integrase-based sensor and memory device was operated by two representative soil Pseudomonads— Pseudomonas fluorescens SBW25 and Pseudomonas putida DSM 291. Quantitative comparisons were made between these two non-traditional hosts and two benchmark E. coli chassis including the probiotic Nissle 1917 and common cloning strain DH5α. The performance of sensor and memory components changed according to each host, such that a clear chassis effect was observed and quantified. These results were obtained via fluorescence from reporter proteins that were transcriptionally fused to the integrase and downstream recombinant region and via data-driven kinetic models. The Pseudomonads proved to be acceptable chassis for the operation of this event logger, which outperformed the common E. coli DH5α in many ways. This study advances an emerging frontier in synthetic biology that aims to build broad-host-range devices and understand the context by which different species can execute programmable genetic operations.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2019

(Bi 0.2 Sb 0.8 ) 2 Te 3 based dynamic synapses with programmable spatio-temporal dynamics

Neuromorphic computing has recently emerged as a promising paradigm to overcome the von-Neumann bottleneck and enable orders of magnitude improvement in bandwidth and energy efficiency. However, existing complementary metal-oxide-semiconductor (CMOS) digital devices, the building block of our computing system, are fundamentally different from the analog synapses, the building block of the biological neural network—rendering the hardware implementation of the artificial neural networks (ANNs) not scalable in terms of area and power, with existing CMOS devices. In addition, the spatiotemporal dynamic, a crucial component for cognitive functions in the neural network, has been difficult to replicate with CMOS devices. Here, we present the first topological insulator (TI) based electrochemical synapse with programmable spatiotemporal dynamics, where long-term and short-term plasticity in the TI synapse are achieved through the charge transfer doping and ionic gating effects, respectively. We also demonstrate basic neuronal functions such as potentiation/depression and paired-pulse facilitation with high precision (>500 states per device), as well as a linear and symmetric weight update. We envision that the dynamic TI synapse, which shows promising scaling potential in terms of energy and speed, can lead to the hardware acceleration of truly neurorealistic ANNs with superior cognitive capabilities and excellent energy efficiency.

36 MATERIALS SCIENCE↗
NASA NTRS2017

Digital Device Architecture and the Safe Use of Flash Devices in Munitions

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

Katz, Richard B.↗
NASA NTRS2007

Filling the Assurance Gap on Complex Electronics

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Plastow, Richard A.↗
DOE OSTI2019

The JET upgraded toroidal Alfvén Eigenmode Diagnostic System

The Alfvén Eigenmode Active Diagnostic system (AEAD) has undergone a major upgrade and redesign to provide a state-of-the-art excitation and real-time detection system for JET. The new system consists of individual 4 kW amplifiers allowing for increased current, separate excitation and real time control of relative phasing between antenna currents. The amplifiers have a frequency range of 10–1000 kHz, divided into various frequency bands by external matching filters. Due to the varying transmission line impedance throughout the frequency range, the amplifiers were designed with a very high resilience to reflected power. The existing amplifier control electronics have been replaced with a digital control system incorporating a National Instruments platform and Field Programmable Gate Array (FPGA) modules for frequency, gain and phase control with a frequency and phase resolution of less than 1 kHz and 1 degree respectively. Complementing the digital control system is the Protection and Control System, which utilizes Field Programmable Analog Arrays (FPAAs) and an array of electronic devices to monitor and control the AEAD. New capabilities such as independent antenna current/phase control, allow for improved excitation control, better definition of antenna spectrum combined with enhanced system reliability. This paper will review the new AEAD system, its unique capabilities and improvements over the previous diagnostic system.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2018

A programmable two-qubit quantum processor in silicon

Now that it is possible to achieve measurement and control fidelities for individual quantum bits (qubits) above the threshold for fault tolerance, attention is moving towards the difficult task of scaling up the number of physical qubits to the large numbers that are needed for fault-tolerant quantum computing (1,2). In this context, quantum-dot-based spin qubits could have substantial advantages over other types of qubit owing to their potential for all-electrical operation and ability to be integrated at high density onto an industrial platform (3,4,5). Initialization, readout and single- and two-qubit gates have been demonstrated in various quantum-dot-based qubit representations (6,7,8,9). However, as seen with small-scale demonstrations of quantum computers using other types of qubit (10,11,12,13), combining these elements leads to challenges related to qubit crosstalk, state leakage, calibration and control hardware. We overcome these challenges by using carefully designed control techniques to demonstrate a programmable two-qubit quantum processor in a silicon device that can perform the Deutsch–Josza algorithm and the Grover search algorithm—canonical examples of quantum algorithms that outperform their classical analogues. We characterize the entanglement in our processor by using quantum-state tomography of Bell states, measuring state fidelities of 85–89 per cent and concurrences of 73–82 per cent. These results pave the way for larger-scale quantum computers that use spins confined to quantum dots.

77 NANOSCIENCE AND NANOTECHNOLOGY↗