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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2010

Automatic control of clock duty cycle

In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.

Feng, Xiaoxin↗
NASA NTRS2019

Coilgun Acceleration Model Containing Multiple Interacting Coils

A coilgun operates by pulsing current through an axially-arranged series of independently-controlled coils inductively interacting with a small, electrically-conductive, azimuthally-symmetric projectile to accelerate it to high velocities. The electrical circuits are programmed to pulse current through the coils in such a way so as to impart further electromagnetic acceleration in each stage. A method is developed to calculate the mutual inductance between the coils and between each coil and the projectile. These terms are used to write a system of first-order ordinary differential equations governing the projectile velocity and the current flow in each coil. While the inclusion of the electromagnetic interactions between coils significantly complicates the equation set as more coil sets are included in the problem, casting the problem symbolically in mass matrix form permits solution using standard numerical Runge-Kutta techniques. Comparing a projectile with a single-turn to that comprised of nine-turns, the inductance of the former is much smaller, but this leads to a greater induced projectile current. The lower inductance and greater current appear to offset each other with little difference in the acceleration profile for the two cases. For the limited cases studied, coils with a discharge half-cycle equal to the time for a projectile to transit from one coil to the next yield increased efficiency.

Polzin, Kurt A.↗
NASA NTRS1989

Method and apparatus for measuring frequency and phase difference

A system for deriving direct digital indications of frequency and phase difference between two incoming pulse trains adaptable for collision avoidance systems or the like. A pair of radar beams 152 and 152A are directed toward a target 153 and corresponding beams 154 and 154A returning therefrom are detected. A digital difference circuit 110 forms a pulse train 66 from the Doppler shift frequencies of each beam pair having a repetition rate functionally related to the difference in magnitude of the shift frequencies. Pulses from the pulse train are counted as a function of time. Visual indications thereof on display 144 are correlative to target position relative to beams 152 and 152A.

Kobayashi, Herbert S.↗
DOE OSTI2020

Extending XACC for Quantum Optimal Control

Quantum computing vendors are beginning to open up application programming interfaces for direct pulse-level quantum control. With this, programmers can begin to describe quantum kernels of execution via sequences of arbitrary pulse shapes. This opens new avenues of research and development with regards to smart quantum compilation routines that enable direct translation of higher-level digital assembly representations to these native pulse instructions. In this work, we present an extension to the XACC system-level quantum-classical software framework that directly enables this compilation lowering phase via user-specified quantum optimal control techniques. This extension enables the translation of digital quantum circuit representations to equivalent pulse sequences that are optimal with respect to the backend system dynamics. Our work is modular and extensible, enabling third party optimal control techniques and strategies in both C++ and Python. We demonstrate this extension with familiar gradient-based methods like gradient ascent pulse engineering (GRAPE), gradient optimization of analytic controls (GOAT), and Krotov's method. Our work serves as a foundational component of future quantum-classical compiler designs that lower high-level programmatic representations to low-level machine instructions.

Nguyen, Thien↗
NASA NTRS1980

Pulse transducer with artifact signal attenuator

An artifact signal attenuator for a pulse rate sensor is described. The circuit for attenuating background noise signals is connected with a pulse rate transducer which has a light source and a detector for light reflected from blood vessels of a living body. The heart signal provided consists of a modulated dc signal voltage indicative of pulse rate. The artifact signal resulting from light reflected from the skin of the body comprises both a constant dc signal voltage and a modulated dc signal voltage. The amplitude of the artifact signal is greater and the frequency less than that of the heart signal. The signal attenuator circuit includes an operational amplifier for canceling the artifact signal from the output signal of the transducer and has the capability of meeting packaging requirements for wrist-watch-size packages.

Cash, W. H., Jr.↗
NASA NTRS1988

Programmable Pulser

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

Baumann, Eric↗
NASA NTRS1989

External electro-optic probing of millimeter-wave integrated circuits

An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

Whitaker, J. F.↗
NASA NTRS1989

External electro-optic probing of millimeter-wave integrated circuits

An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

Whitaker, J. F.↗
NASA NTRS1965

5KW pulse width modulated static inverter

Design verification tests for logic and low level circuits, and preliminary single-phase breadboard of pulse width modulated static inverter

PULSE WIDTH MODULATION /PWM/↗
DOE OSTI2023

Direct current momentary circuit interrupter

A momentary circuit interrupter in series connection with a mechanical switch to provide protection against short circuit faults in a DC power circuit. The momentary circuit interrupter injects a transient voltage pulse via a pulse transformer to reduce a DC fault current to near zero in a DC circuit branch, thus allowing the mechanical switch to disconnect the faulty branch under a near zero-current condition. The power electronic circuit on the primary side of the transformer controls the discharge of a plurality of pre-charged capacitors to generate the transient voltage pulse during the fault interruption process, but otherwise does not incur any power loss during normal operation. The secondary winding of the pulse transformer conducts the main DC current, and is highly conductive to minimize the conduction power loss. The invention provides ultrafast response to a short circuit fault (even faster than solid-state circuit breakers and much faster than hybrid circuit breakers), significantly reduced overcurrent stress in the power system, and/or ultralow conduction power losses.

Shen, Zheng John↗
NASA NTRS2008

System and method for determining velocity of electrically conductive fluid

A flowing electrically-conductive fluid is controlled between an upstream and downstream location thereof to insure that a convection timescale of the flowing fluid is less than a thermal diffusion timescale of the flowing fluid. First and second nodes of a current-carrying circuit are coupled to the fluid at the upstream location. A current pulse is applied to the current-carrying circuit so that the current pulse travels through the flowing fluid to thereby generate a thermal feature therein at the upstream location. The thermal feature is convected to the downstream location where it is monitored to detect a peak associated with the thermal feature so-convected. The velocity of the fluid flow is determined using a time-of-flight analysis.

Polzin, Kurt A.↗
DOE OSTI2024

High power pulse systems for surface processing

A high-power pulsed surface processing system includes insulated-gate bipolar transistors (IGBT) to replicate desirable pulse structures with high precision, at low cost, and with high reliability within a single system. The pulsed surface processing system includes a power supply, an anode and a cathode, a dual gate driver supplying power to one or more IGBT gates, and one or more capacitor banks. Pulse formation software controls the timing and duration of electrical pulses to the electrodes. A freewheeling diode protects the system from an abrupt reduction of current in the circuit. The high-power pulsed surface processing system may be used to control versatile and complex pulse structures while with precise control of instantaneous pulse powers, pulse timing, and process control. The inclusion of dual gate drivers also offers the ability for multiple pulsers to be created and “slaved” together for a wide variety of custom processes.

Tian, Hui↗
NASA NTRS2012

Wide Range SET Pulse Measurement

A method for measuring a wide range of SET pulses is demonstrated. Use of dynamic logic, faster than ordinary CMOS, allows capture of short pulses. A weighted binning of SET lengths allows measurement of a wide range of pulse lengths with compact circuitry. A pulse-length-conservative pulse combiner tree routes SETs from combinational logic to the measurement circuit, allowing SET measurements in circuits that cannot easily be arranged in long chains. The method is applied to add-multiplex combinational logic, and to an array of NFET routing switches, at .35 micron. Pulses are captured in a chain of Domino Logic AND gates. Propagation through the chain is frozen on the trailing edge by dropping low the second "enable" input to the AND gates. Capacitive loading is increased in the latter stages to create an approximately logarithmic weighted binning, so that a broad range of pulse lengths can be captured with a 10 stage capture chain. Simulations show pulses can be captured which are 1/5th the length of those typically captured with leading edge triggered latch methods, and less than the length of those captured with a trailing edge latch method. After capture, the pulse pattern is transferred to an SEU protected shift register for readout. 64 instances of each of two types of logic are used as targets. One is a full adder with a 4 to 1 mux on its inputs. The other is a 4 x 4 NFET routing matrix. The outputs are passed through buffered XNOR comparators to identify pulses, which are merged in a buffered not-nand (OR) tree designed to avoid pulse absorption as much as possible. The output from each of the two test circuits are input into separate pulse measurement circuits. Test inputs were provided so that the circuit could be bench tested and calibrated. A third SET measurement circuit with no inputs was used to judge the contribution from direct hits on the measurement circuit. Heavy ions were used with an LET range from 12 to 176. At LET of 21 and below, the very small number of SETs were not significantly higher in the test over the control circuits. At higher LET the test circuit SETs are one or two orders of magnitude greater than for the control circuit. The NFET circuit produces more and slightly longer SETs as expected. But the differences do not appear to be significant enough to modify strategies now used to avoid capture of SETs in chips such as FPGAs. Complete data and graphs will be in the full paper / presentation. In the summary figure below left, NOCL is the reference circuit without any input, and number of stages triggered is plotted. Simulation at right shows the smallest pulse captured (stage 2) at about 300 ps. Our conclusion is that the method is promising, but that improvements in the merge network are desirable before applying in a deep submicron process

Shuler, Robert L.↗
NASA NTRS1973

ASDTIC control and standardized interface circuits applied to buck, parallel and buck-boost dc to dc power converters

Versatile standardized pulse modulation nondissipatively regulated control signal processing circuits were applied to three most commonly used dc to dc power converter configurations: (1) the series switching buck-regulator, (2) the pulse modulated parallel inverter, and (3) the buck-boost converter. The unique control concept and the commonality of control functions for all switching regulators have resulted in improved static and dynamic performance and control circuit standardization. New power-circuit technology was also applied to enhance reliability and to achieve optimum weight and efficiency.

Schoenfeld, A. D.↗
NASA NTRS1985

Pulse width modulation inverter with battery charger

An inverter is connected between a source of DC power and a three-phase AC induction motor, and a microprocessor-based circuit controls the inverter using pulse width modulation techniques. In the disclosed method of pulse width modulation, both edges of each pulse of a carrier pulse train are equally modulated by a time proportional to sin .theta., where .theta. is the angular displacement of the pulse center at the motor stator frequency from a fixed reference point on the carrier waveform. The carrier waveform frequency is a multiple of the motor stator frequency. The modulated pulse train is then applied to each of the motor phase inputs with respective phase shifts of 120.degree. at the stator frequency. Switching control commands for electronic switches in the inverter are stored in a random access memory (RAM) and the locations of the RAM are successively read out in a cyclic manner, each bit of a given RAM location controlling a respective phase input of the motor. The DC power source preferably comprises rechargeable batteries and all but one of the electronic switches in the inverter can be disabled, the remaining electronic switch being part of a flyback DC-DC converter circuit for recharging the battery.

Slicker, James M.↗