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Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.
We assess the availability of nutrient elements, energy and liquid water on the plains surrounding Columbia Memorial Station by evaluating data from Spirit in the context of previous Mars missions, Earth-based studies of martian meteorites and studies of microbial communities on Earth that represent potential analogs of martian biota. The compositions of Gusev basalts resemble those of olivine basalts beneath the seabed on Earth that deep drilling has shown to support life. Of particular relevance to biology, phosphate abundances are much greater in Gusev basalts (0.84 +/- 0.07 wt. % P2O5) than in oceanic basalts (typically 0.06 wt. %).
BACKGROUND Spaceflight-associated immune dysregulation (SAID) occurs during spaceflight and may represent specific clinical risks for exploration-class missions. An appropriate ground analog for spaceflight-associated immune dysregulation would offer a platform for ground-evaluation of various potential countermeasures. This study evaluated the NASA Undersea Mission Operations ( NEEMO ), consisting of 14 day undersea deployment at the Aquarius station, as an analog for SAID. Sixteen Aquanauts from missions NEEMO-12, 13 and 14 participated in the study. RESULTS Mid-mission alterations leukocyte distribution occurred, including granulocytosis and elevations in central-memory CD8+ T-cells. General T cell function was reduced during NEEMO missions in roughly 50% of subjects. Secreted cytokines profiles were evaluated following whole blood stimulation with CD3/CD28 (T cells) or LPS (monocytes). T cell production of IFNg, IL-5, IL-10, IL-2, TNFa and IL-6 were all reduced before and during the mission. Conversely, monocyte production of TNFa, IL-10, IL-6, IL-1b and IL-8 were elevated during mission, moreso at the MD-14 timepoint. Antibodies to Epstein-Barr virus (EBV) viral capsid antigen and early antigen were increased in approximately 40% of the subjects. Changes in EBV tetramer-positive CD8+ T-cells exhibited a variable pattern. Antibodies against Cytomegalovirus (CMV) were marginally increased during the mission. Herpesvirus reactivation was determined by PCR. EBV viral load was generally elevated at L-6. Higher levels of salivary EBV were found during the NEEMO mission than before and after as well as than the healthy controls. No VZV or CMV was found in any pre, during and after NEEMO mission or control samples. Plasma cortisol was elevated at L-6. CONCLUSION Unfortunately, L-6 may be too near to mission start to be an appropriate baseline measurement. The general immune changes in leukocyte distribution, T cell function, cytokine production, virus specific immunity and viral reactivation are similar to those observed during or following spaceflight. The NEEMO platform may thus have utility for short-duration, ground-based spaceflight-immune research, such as investigations of mechanism or countermeasures validation.
The Ultra-Fast X-ray Imager (UXI) program is an ongoing effort at Sandia National Laboratories to create high speed, multi-frame, time-gated Read Out Integrated Circuits (ROICs), and a corresponding suite of photodetectors to image a wide variety of High Energy Density (HED) physics experiments on both Sandia’s Z-Machine and LLNL’s National Ignition Facility (NIF). Several cameras have been designed over the length of the program; one of the most recent is the Icarus, which is an improvement on past imagers (Furi and Hippogriff). A second sensor that can be connected is the Daedalus sensor. The Icarus is a 1024 × 512-pixel array with either 25 μm or 8 µm spatial resolution containing four frames of storage per pixel and has improved timing generation and distribution components while achieved 2 ns time gating. The Daedalus sensor is also a 1024 x 512-pixel array with 25 µm special resolution containing three frames of storage per pixel and has an increased set of features for a wider variety of applications from interlacing of rows in each frame to configurability of all shutters. See Section 14 for details regarding the Icarus implementation of the firmware and Section 15 for details regarding the Daedalus implementation. Due to the unique test environments UXI sensors are targeted for, full custom hardware was required to physically mount an Icarus or Daedalus sensor, manage its various functions, and read out pixel data for transfer to a host computer. Beyond experimental functionality, the hardware also needed to accommodate sensor characterization requirements. Lawrence Livermore National Laboratory’s ‘Version 4.0 Board’ was the result of these efforts. It mounts all the components required to fully utilize the Icarus and Daedalus sensors including analog to digital converters to convert pixel data and various system voltages to digital form for readout and analysis, DAC channels for remote configuration of critical bias voltages, static random-access memories to buffer pixel data, RS422 and Gigabit Ethernet communications for remote access, and an FPGA to tie these components together. This document describes the FPGA electrical interfaces in detail to allow the reader a greater understanding of the device, and to facilitate implementation of custom software to control and manage it. The Version 4.0 Board is a continuation of the Nano-second Gated CMOS hardware design that retains much of the functionality of the Version 1.0 Board while adding features including a DAC instead of digital potentiometers, as well as sensors for pressure and radiation. The Version 4.0 board is intended for applications requiring tight form-factor enclosures. It is composed of two stacking boards; one holds the FPGA and regulators to power the various components of the board while the other contains the mating connector to the sensor, image-readoff ADCs, the DAC, and other components.
Changes in synapse weights due to circuit drifts suppressed. Proposed fully parallel analog version of electronic neural-network processor based on delta-back-propagation algorithm. Processor able to "learn" when provided with suitable combinations of inputs and enforced outputs. Includes programmable resistive memory elements (corresponding to synapses), conductances (synapse weights) adjusted during learning. Buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in layers of electronic neurons in accordance with delta-back-propagation algorithm.
Ice buildup on aircraft leading edge surfaces has historically been a problem. Most conventional deicing systems rely either on surface heating to melt the accreted ice or pneumatic surface inflation to mechanically debond the ice. Deicers that rely solely on surface heating require large amounts of power. Pneumatic deicers usually cannot remove thin layers of ice and lack durability. Thus, there is a need for an advanced, low-power ice protection system. As part of the NASA Small Business and Innovation Research (SBIR) program, Innovative Dynamics, Inc., developed an aircraft deicing system that utilizes the properties of Shape Memory Alloys (SMA). The SMA-based system has achieved promising improvements in energy efficiency and durability over more conventional deicers. When they are thermally activated, SMA materials change shape; this is analogous to a conventional thermal expansion. The thermal input is currently applied via conventional technology, but there are plans to implement a passive thermal input that is supplied from the energy transfer due to the formation of the ice itself. The actively powered deicer was tested in the NASA Lewis Icing Research Tunnel on a powered rotating rig in early 1995. The system showed promise, deicing both rime and glaze ice shapes as thin as 1/8 in. The first prototype SMA deicer reduced power usage by 45 percent over existing electrothermal systems. This prototype system was targeted for rotorcraft system development. However, there are current plans underway to develop a fixed-wing version of the deicer.
Compute In-Memory platforms such as memristive crossbars are gaining focus as they facilitate acceleration of Deep Neural Networks (DNNs) with high area and compute efficiencies. However, the intrinsic non-idealities associated with the analog nature of computing in crossbars limits the performance of the deployed DNNs. Furthermore, DNNs are shown to be vulnerable to adversarial attacks leading to severe security threats in their large-scale deployment. Thus, finding adversarially robust DNN architectures for non-ideal crossbars is critical to the safe and secure deployment of DNNs on the edge. This work proposes a two-phase algorithm-hardware co-optimization approach called XploreNAS that searches for hardware efficient and adversarially robust neural architectures for non-ideal crossbar platforms. We use the one-shot Neural Architecture Search approach to train a large Supernet with crossbar-awareness and sample adversarially robust Subnets therefrom, maintaining competitive hardware efficiency. Our experiments on crossbars with benchmark datasets (SVHN, CIFAR10, CIFAR100) show up to ~8–16% improvement in the adversarial robustness of the searched Subnets against a baseline ResNet-18 model subjected to crossbar-aware adversarial training. We benchmark our robust Subnets for Energy-Delay-Area-Products (EDAPs) using the Neurosim tool and find that with additional hardware efficiency–driven optimizations, the Subnets attain ~1.5–1.6× lower EDAPs than ResNet-18 baseline.
Supervisory Control and Data Acquisition (SCADA) systems are utilized extensively in critical power grid infrastructures. Modern SCADA systems have been proven to be susceptible to cyber-security attacks and require improved security primitives in order to prevent unwanted influence from an adversarial party. One section of weakness in the SCADA system is the integrity of field level sensors providing essential data for control decisions at a master station. In this paper we propose a lightweight hardware scheme providing inferred authentication for SCADA sensors by combining an analog to digital converter and a permutation generator as a single integrated circuit. Through this method we encode critical sensor data at the time of sensing, so that unencoded data is never stored in memory, increasing the difficulty of software attacks. We show through experimentation how our design stops both software and hardware false data injection attacks occurring at the field level of SCADA systems.
The computational requirements and basic features of strapdown gyroscopes for inertial navigation are discussed. Strapdown navigators currently require 20 to 50% of the available time of a minicomputer with a capability of several hundred thousand operations per second; memory requirements are 2000 to 3000 16-bit words. A system in which these computational demands are met by three limited capability microcomputers is described. A technique using dedicated microprocessors in the place of analog electronics in the gyroscope control loops is discussed, and attention is given to applications of microprocessor technology in redundant strapdown navigation systems and associated flight control systems.
This report assesses the availability of nutrient elements, energy and liquid water on the plains surrounding Columbia Memorial Station by evaluating observations by the MER rover Spirit in the context of previous Mars missions, Earth-based studies of martian meteorites and studies of microbial communities on Earth that represent potential analogs of martian biota.
The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.
Signals combined with minimal noise by use of sums in read-only memories. Signals from subscribers A and B digitized, transmitted, and combined by addressing ROM. Combining operation electronic equivalent of looking up value of function of two variables in mathematical table. Combined digitized signal transmitted, converted to analog form, and delivered to subscriber C. System intended especially for combining number of separate audio signals into one signal for retransmission, as in telephone conference calling.
In recent years, hardware-in-the-loop (HIL) testing has carved a strong niche in several industries, such as automotive, aerospace, telecomm, and consumer electronics. As desktop computers have realized gains in speed, memory size, and data storage capacity, hardware/software platforms have evolved into high performance, deterministic HIL platforms, capable of hosting the most demanding applications for testing components and subsystems. Using simulation software to emulate the digital and analog I/O signals of system components, engineers of all disciplines can now test new systems in realistic environments to evaluate their function and performance prior to field deployment. Within the Aerospace industry, space-borne satellite systems are arguably some of the most demanding in terms of their requirement for custom engineering and testing. Typically, spacecraft are built one or few at a time to fulfill a space science or defense mission. In contrast to other industries that can amortize the cost of HIL systems over thousands, even millions of units, spacecraft HIL systems have been built as one-of-a-kind solutions, expensive in terms of schedule, cost, and risk, to assure satellite and spacecraft systems reliability. The focus of this paper is to present a new approach to HIL testing for spacecraft systems that takes advantage of a highly flexible hardware/software architecture based on National Instruments PXI reconfigurable hardware and virtual instruments developed using LabVIEW. This new approach to HIL is based on a multistage/multimode spacecraft bus emulation development model called Reconfigurable Hardware In-the-Loop or RHIL.
The invention discloses a system capable of memorizing maximum sensed values. The system includes conditioning circuitry which receives the analog output signal from a sensor transducer. The conditioning circuitry rectifies and filters the analog signal and provides an input signal to a digital driver, which may be either linear or logarithmic. The driver converts the analog signal to discrete digital values, which in turn triggers an output signal on one of a plurality of driver output lines n. The particular output lines selected is dependent on the converted digital value. A microfuse memory device connects across the driver output lines, with n segments. Each segment is associated with one driver output line, and includes a microfuse that is blown when a signal appears on the associated driver output line.
The invention discloses a system capable of memorizing maximum sensed values. The system includes conditioning circuitry which receives the analog output signal from a sensor transducer. The conditioning circuitry rectifies and filters the analog signal and provides an input signal to a digital driver, which may be either liner or logarithmic. The driver converts the analog signal to discrete digital values, which in turn triggers an output signal on one of a plurality of driver output lines n. The particular output lines selected is dependent on the converted digital value. A microfuse memory device connects across the driver output lines, with n segments. Each segment is associated with one driver output line, and includes a microfuse that is blown when a signal appears on the associated driver output line.
SpaceCube 1.5 is a high-performance and low-power system in a compact form factor. It is a hybrid processing system consisting of CPU (central processing unit), FPGA (field-programmable gate array), and DSP (digital signal processor) processing elements. The primary processing engine is the Virtex- 5 FX100T FPGA, which has two embedded processors. The SpaceCube 1.5 System was a bridge to the SpaceCube 2.0 and SpaceCube 2.0 Mini processing systems. The SpaceCube 1.5 system was the primary avionics in the successful SMART (Small Rocket/Spacecraft Technology) Sounding Rocket mission that was launched in the summer of 2011. For SMART and similar missions, an avionics processor is required that is reconfigurable, has high processing capability, has multi-gigabit interfaces, is low power, and comes in a rugged/compact form factor. The original SpaceCube 1.0 met a number of the criteria, but did not possess the multi-gigabit interfaces that were required and is a higher-cost system. The SpaceCube 1.5 was designed with those mission requirements in mind. The SpaceCube 1.5 features one Xilinx Virtex-5 FX100T FPGA and has excellent size, weight, and power characteristics [4×4×3 in. (approx. = 10×10×8 cm), 3 lb (approx. = 1.4 kg), and 5 to 15 W depending on the application]. The estimated computing power of the two PowerPC 440s in the Virtex-5 FPGA is 1100 DMIPS each. The SpaceCube 1.5 includes two Gigabit Ethernet (1 Gbps) interfaces as well as two SATA-I/II interfaces (1.5 to 3.0 Gbps) for recording to data drives. The SpaceCube 1.5 also features DDR2 SDRAM (double data rate synchronous dynamic random access memory); 4- Gbit Flash for storing application code for the CPU, FPGA, and DSP processing elements; and a Xilinx Platform Flash XL to store FPGA configuration files or application code. The system also incorporates a 12 bit analog to digital converter with the ability to read 32 discrete analog sensor inputs. The SpaceCube 1.5 design also has a built-in accelerometer. In addition, the system has 12 receive and transmit RS- 422 interfaces for legacy support. The SpaceCube 1.5 processor card represents the first NASA Goddard design in a compact form factor featuring the Xilinx Virtex- 5. The SpaceCube 1.5 incorporates backward compatibility with the Space- Cube 1.0 form factor and stackable architecture. It also makes use of low-cost commercial parts, but is designed for operation in harsh environments.
A NASA-directed development of massively parallel processor (MPP) computers is outlined, noting intended applications for data processing for near term earth resource and environment mapping, radar, and television transmissions. The MPP is designed to perform 100 billion operations/sec to obtain satisfactory image processing, while separate processing units correct distortions, register images, calculate correlation functions, and classify multispectral characteristics. Arrays of 1s and 0s will be manipulated in analog-to-digital conversions generating separate planes corresponding to powers of binaries. Data wires are replaced by fiber-optic tubes or thousands of wires, and single logic gates are replaced by thousands of logic gates and every memory element by thousands of memory elements. Features of the interconnections and the images control processor units are detailed, along with implementation of sliders for program flexibility.
A blueprint for a protocell was presented in 1960 (Fox) as a consequence of the newly discovered self-ordering of amino acids and the self-organization of the resultant thermal proteins into cellular structures. The biofunctions of the laboratory protocells (proteinoid microspheres) have since been cataloged; they display roots of many phenomena of modern cells, e.g. synthesis of internucleotide and peptide bonds in aqueous media. These results are inconsistent with a popular assumption that DNA/RNA preceded protein in earliest molecular evolution. The necessity for synthetic research on molecules and cells to 'begin at the beginning' is being realized. Ivanov and Fortsch (1986) have described by analysis how the self-ordering mechanism of amino acids into informed thermal proteins was conserved in evolution from the earliest stage as modern (reverse) mechanisms assumed control. Tyagi and Ponnamperuma (1990) have negated assumptions corollary to DNA/RNA. Ponnamperuma has demonstrated the powerful effect of self-ordering of amino acids in polymerization of aminoacyl nucleotides and the irrelevance of mononucleotide residues. Excitable thermal proteins (Vaughan et al, 1987) are neurotrophic and antiaging when added to cultures of real neurons (Hefti et al, 1991) and are memory enhancers in mice (Fox and Flood, 1992). Proteinoid microspheres of dominant hydrophobic constitution form 'gap junctions', sprout axon-like outgrowths, and form dendritic networks spontaneously. In the latest studies, phenylalanine-rich equimolar proteinoid or the leucine analog (Ishima et al 1981), is found to produce electrical signals for several days when lecithin is included in the assembly with the thermal polymer.