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At least 217 records · Page 12

A high-speed photonic clock and carrier regenerator

As data communications rates climb toward 10 Gbits/s, clock recovery and synchronization become more difficult, if not impossible, using conventional electronic circuits. The high-speed photonic clock regenerator described in this article may be more suitable for such use. This photonic regenerator is based on a previously reported photonic oscillator capable of fast acquisition and synchronization. With both electrical and optical clock inputs and outputs, the device is easily interfaced with fiber-optic systems. The recovered electrical clock can be used locally and the optical clock can be used anywhere within a several kilometer radius of the clock/carrier regenerator.

Yao, X. S.↗

Global synchronization algorithms for the Intel iPSC/860

In a distributed memory multicomputer that has no global clock, global processor synchronization can only be achieved through software. Global synchronization algorithms are used in tridiagonal systems solvers, CFD codes, sequence comparison algorithms, and sorting algorithms. They are also useful for event simulation, debugging, and for solving mutual exclusion problems. For the Intel iPSC/860 in particular, global synchronization can be used to ensure the most effective use of the communication network for operations such as the shift, where each processor in a one-dimensional array or ring concurrently sends a message to its right (or left) neighbor. Three global synchronization algorithms are considered for the iPSC/860: the gysnc() primitive provided by Intel, the PICL primitive sync0(), and a new recursive doubling synchronization (RDS) algorithm. The performance of these algorithms is compared to the performance predicted by communication models of both the long and forced message protocols. Measurements of the cost of shift operations preceded by global synchronization show that the RDS algorithm always synchronizes the nodes more precisely and costs only slightly more than the other two algorithms.

Seidel, Steven R.↗

A Novel Photonic Clock and Carrier Recovery Device

As data communication rates climb toward ten Gb/s, clock recovery and synchronization become more difficult, if not impossible, using conventional electronic circuits. We present in this article experimental results of a high speed clock and carrier recovery using a novel device called a photonic oscillator that we recently developed in our laboratory. This device is capable of recovering clock signals up to 70 GHz. To recover the clock, the incoming data is injected into the photonic oscillator either through the optical injection port or the electrical injection port. The free running photonic oscillator is tuned to oscillate at a nominal frequency equal to the clock frequency of the incoming data. With the injection of the data, the photonic oscillator will be quickly locked to clock frequency of the data stream while rejecting other frequency components associated with the data. Consequently, the output of the locked photonic oscillator is a continuous periodical wave synchronized with the incoming data or simply the recovered clock. We have demonstrated a clock to spur ratio of more than 60 dB of the recovered clock using this technique. Similar to the clock recovery, the photonic oscillator can be used to recover a high frequency carrier degraded by noise and an improvement of about 50 dB in signal-to-noise ratio was demonstrated. The photonic oscillator has both electrical and optical inputs and outputs and can be directly interfaced with a photonic system without signal conversion. In addition to clock and carrier recovery, the photonic oscillator can also be used for (1) stable high frequency clock signal generation, (2) frequency multiplication, (3) square wave and comb frequency generation, and (4) photonic phase locked loop.

Yao, X. Steve↗

Recent Progress at the International Laser Ranging Service (ILRS)

The International Laser Ranging Service (ILRS) is experiencing significant growth. New stations are being built and brought into operation, expanding the spatial and temporal coverage of the Satellite Laser Ranging (SLR) observations. Some of these stations are multi-technique Core Sites that allow us to exploit the combined strengths of different geodetic space techniques. New satellites are strengthening the ILRS contribution to the International Terrestrial Reference Frame (ITRF), and expanding the spectrum of satellite applications supported by the ILRS. New analysis, modeling, and data processing techniques continue to improve the science products. New campaigns are continuing to expand SLR applications into relativity and the study of non-gravitational forces. The ILRS is currently participating in the Galileo for Science campaign (G4S_2.0 project), funded by the Italian Space Agency (ASI), which aims to perform a set of measurements in the field of gravitation with the Galileo satellites, taking advantage of the accuracy of the on-board atomic clocks and, in particular, of GSAT0201and GSAT0202 by exploiting their relatively high eccentricity (~0.16). New activities underway in Lunar Laser Ranging (LLR), with the imminent launch and deployment of the upcoming Next Generation Lunar Retroreflector - 1 (NGLR-1) to the lunar surface. Some new satellites supported by the ILRS are now exploring means of capturing Space Debris, while some ILRS stations run local laser ranging projects to track space debris, contributing to the maintenance of various data catalogs. Time transfer experiments are also expanding the application of laser ranging, linking two fully characterized optical clocks at different locations with SLR (Einstein Synchronization) providing measurements of height differences, demonstrating the feasibility of a physical height system. Two-way and one-way transponders activity has been underway since the LASSO experiment in the 1990’s. More experiments are underway or planned. Applications include time and frequency transfer and clock synchronization between ground and space, interplanetary laser ranging, and fundamental physics. This presentation will give an update on ILRS activities and the impact that these activities have had and will have on ILRS data products.

Lunar Laser Ranging↗

Atomic and gravitational clocks

Atomic and gravitational clocks are governed by the laws of electrodynamics and gravity, respectively. While the strong equivalence principle (SEP) assumes that the two clocks have been synchronous at all times, recent planetary data seem to suggest a possible violation of the SEP. Past analysis of the implications of an SEP violation on different physical phenomena revealed no disagreement. However, these studies assumed that the two different clocks can be consistently constructed within the framework. The concept of scale invariance, and the physical meaning of different systems of units, are now reviewed and the construction of two clocks that do not remain synchronous - whose rates are related by a non-constant function beta sub a - is demonstrated. The cosmological character of beta sub a is also discussed.

Canuto, V. M.↗

A synchronous motor chopper for laboratory testing of detector systems in infrared astronomy

Airborne and ground-based IR telescopes have oscillating secondary mirrors to permit subtraction of background emission from the sky and telescope. These chopping mirrors are synchronized to a clock which may originate in the data acquisition system. For laboratory testing of detecting instruments with such data systems, externally synchronized chopped IR sources are required. We describe a laboratory chopper in which a synchronous motor is driven by 2-phase sinusoidal currents in sync with an external clock at frequencies from 5 to 50 Hz. This design is used with the KAO's facility sources, the Chopped Hotplate and the Portable Chopped Light Source (PCLS).

Baltz, James A.↗

A Timer for Synchronous Digital Systems

The Real-Time Interferometer Control Systems Testbed (RICST) timing board is a VersaModule Eurocard (VME)-based board that can generate up to 16 simultaneous, phase-locked timing signals at a rate defined by the user. It can also generate all seven VME interrupt requests (IRQs). The RICST timing board is suitable mainly for robotic, aerospace, and real-time applications. Several circuit boards on the market are capable of generating periodic IRQs. Most are associated with Global Positioning System (GPS) receivers and Inter Range Instrumentation Group (IRIG) time-code generators, whereas this board uses either an internal VME clock or an externally generated clock signal to synchronize multiple components of the system. The primary advantage of this board is that there is no discernible jitter in the output clock waveforms because the signals are divided down from a high-frequency clock signal instead of being phase-locked from a lower frequency. The primary disadvantage to this board, relative to other periodic-IRQ-generating boards, is that it is more difficult to synchronize the system to wall clock time.

McKenney, Elizabeth↗

GPS-Based Navigation and Orbit Determination for the AMSAT Phase 3D Satellite

This paper summarizes the results of processing GPS data from the AMSAT Phase 3D (AP3) satellite for real-time navigation and post-processed orbit determination experiments. AP3 was launched into a geostationary transfer orbit (GTO) on November 16, 2000 from Kourou, French Guiana, and then was maneuvered into its HEO over the next several months. It carries two Trimble TANS Vector GPS receivers for signal reception at apogee and at perigee. Its spin stabilization mode currently makes it favorable to track GPS satellites from the backside of the constellation while at perigee, and to track GPS satellites from below while at perigee. To date, the experiment has demonstrated that it is feasible to use GPS for navigation and orbit determination in HEO, which will be of great benefit to planned and proposed missions that will utilize such orbits for science observations. It has also shown that there are many important operational considerations to take into account. For example, GPS signals can be tracked above the constellation at altitudes as high as 58000 km, but sufficient amplification of those weak signals is needed. Moreover, GPS receivers can track up to 4 GPS satellites at perigee while moving as fast as 9.8 km/sec, but unless the receiver can maintain lock on the signals long enough, point solutions will be difficult to generate. The spin stabilization of AP3, for example, appears to cause signal levels to fluctuate as other antennas on the satellite block the signals. As a result, its TANS Vectors have been unable to lock on to the GPS signals long enough to down load the broadcast ephemeris and then generate position and velocity solutions. AP3 is currently in its eclipse season, and thus most of the spacecraft subsystems have been powered off. In Spring 2002, they will again be powered up and AP3 will be placed into a three-axis stabilization mode. This will significantly enhance the likelihood that point solutions can be generated, and perhaps more important, that the receiver clock can be synchronized to GPS time. This is extremely important for real-time and post-processed orbit determination, where removal of receiver clock bias from the data time tags is needed, for time-tagging of science observations. Current analysis suggests that the inability to generate point solutions has allowed the TANS Vector clock bias to drift freely, being perhaps as large as 5-7 seconds by October, 2001, thus causing up to 50 km of along-track orbit error. The data collected in May, 2002 while in three-axis stabilized mode should provide a significant improvement in the orbit determination results.

Davis, George↗

Ensuring fault tolerance of phase-locked clocks

Processors within a real-time multiprocessor system must be synchronized with as little overhead as possible. Although synchronization can be achieved via both software (e.g., interactive convergence and interactive consistency algorithms) and hardware (e.g., multistage synchronizers and phase-locked clocks), phase-locked clocks are most attractive due to their small overheads. Despite the fact that synchronization of the multiprocessor system with phase-locked clocks is totally different in nature from the interactive consistency algorithm, it is presently proven that it must satisfy the same condition, N equal to or greater than 3m + 1, where N is the total number of clocks in the multiprocessor system and m is the maximum number of faults tolerable. Also presented are results showing how to design phase-locked clocks so as to be impervious up to a given arbitrary number of malicious failures.

Krishna, C. M.↗

Reliable interface design for combining asynchronous and synchronous circuits

In order to successfully integrate asynchronous and synchronous designs, great care must be taken at the interface between the two types of systems. Synchronizing asynchronous inputs with a free running clock can cause well-known problems with metastability in the synchronization circuits. Stretchable clocks allow a clock cycle to expand dynamically in response to the metastability effects of sampling asynchronous inputs. We use an interface organization where the special circuitry for detecting metastability and for stretching the clock that is delivered to the synchronous part of the system is encapsulated in a Q-flop-based interface. This provides a very convenient method for interfacing mixed systems, as the interface and clock generation circuitry are isolated into one special module, and neither the asynchronous nor the synchronous system need be modified internally to accommodate the interface. This is especially important when standard synchronous components are used as there is no opportunity to modify these parts. We show that this interface module is suitable for most mixed design needs and conclude with an example.

Josephson, Lueli↗

Comments on the "Byzantine Self-Stabilizing Pulse Synchronization" Protocol: Counter-examples

Embedded distributed systems have become an integral part of many safety-critical applications. There have been many attempts to solve the self-stabilization problem of clocks across a distributed system. An analysis of one such protocol called the Byzantine Self-Stabilizing Pulse Synchronization (BSS-Pulse-Synch) protocol from a paper entitled "Linear Time Byzantine Self-Stabilizing Clock Synchronization" by Daliot, et al., is presented in this report. This report also includes a discussion of the complexity and pitfalls of designing self-stabilizing protocols and provides counter-examples for the claims of the above protocol.

Malekpour, Mahyar R.↗

A rate-transparent, self-clocking line code

A reliable and economical new transmission code is presented with the following properties: zero dc content, baseband bandwidth conservation, self-clocking capability, and data-rate-transparent decoding and synchronization. Simple encoder/decoder and clock extractor circuits are given. The code is demonstrated in a wavelength-multiplexed fiber-optic communication system.

Prucnal, Paul R.↗

Smart Contracts for Power Grid Applications Using the Advanced DLT Cyber Grid Guard Testbed

In this study is presented two power system applications with distributed ledger technology (DLT) and smart contracts (SC) that were assessed in a Cyber-Grid-Guard System (CGGS) advanced testbed, with protective relays, power meters, communication devices, DLT devices, synchronized time source, clock displays and real time simulator. This CGGS testbed was set in the Advanced Protection Lab, 252 lab space of the Grid Research Integration and Deployment Center (GRID- C), at Oak Ridge National Laboratory. In power grids, customer-owned distributed energy resources (DERs) are more frequent than in the past, and the numbers of points of interconnection (POI) with customer-owned DERs have increased. Disruptive operation from DERs presents a risk to grid operations, and protective relays located at the POI are used to isolate out-of-tolerance or poorly behaving of DERs. Ensuring the integrity of data from the relays at the POI, and DLT could enhance the security of the power grids. The first application is a SC to define and control the allowable total power factor (TPF) of the DER (wind farm) output, and the terms of the SC are implemented using DLT with a CGGS for a customer-owned DER. The TPF SC was implemented by the CGGS using DLT. The experimental model was performed with a real-time simulator using a CGGS and relay in-the-loop. The data collected from the CGGS were used to execute the TPF SC. The TPF limits were between +0.9 and +1.0, and the breakers’ operation in the POI was controlled by the relay using the SC. The events were collected from the real-time simulator, CGGS, and SEL 700GT relay to validate a successful application of the TPF SC using DLT. The second application is a SC to measure and control the allowable voltage service limits (VSL) by the CGGS using DLT. The tests were performed by using a real-time simulator, CGGS and relay in-the-loop. The data was collected from the CGGS that executed the SC. The main constraints were defined based on ANSI C84.1 service voltage limits, and the operation of the breakers in the POI. The events were collected from the CGGS, and SEL 700GT relay to assess a successful operation of the VSL SC using DLT.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Method and apparatus for decoding compatible convolutional codes

This invention relates to learning decoders for decoding compatible convolutional codes. The decoder decodes signals which have been encoded by a convolutional coder and allows performance near the theoretical limit of performance for coded data systems. The decoder includes a sub-bit shift register wherein the received sub-bits are entered after regeneration and shifted in synchronization with a clock signal recovered from the received sub-bit stream. The received sub-bits are processed by a sub-bit decision circuit, entered into a sub-bit shift register, decoded by a decision circuit, entered into a data shift register, and updated to reduce data errors. The bit decision circuit utilizes stored sub-bits and stored data bits to determine subsequent data-bits. Data errors are reduced by using at least one up-date circuit.

Doland, G. D.↗

Instrumentation for one-way satellite PTTI applications

A review of general principles and operational procedures illustrates how the typical passive user and omni receiving antenna can recover Precise Time and Time Interval (PTTI) information from a low altitude navigation satellite system for clock calibration and synchronization. Detailed discussions of concepts and theory of the receiver design are presented. The importance of RF correlation of the received and local PN encoded sequences is emphasized as a means of reducing delay uncertainties of the instrumentation to values compatible with nanosecond to submicrosecond PTTI objectives. Two receiver configurations were fabricated for use in satellite-to-laboratory experiments. In one receiver the delay-locked loop for PN signals synchronization used a dithered amplitude detection process while the second receiver used a complex sums phase detection method for measurement of delay error. The necessity for compensation of Doppler shift is discussed. Differences in theoretical signal acquisition and tracking performance of the design concepts are noted.

Osborne, A. E.↗

Time code dissemination experiment via the SIRIO-1 VHF transponder

An experiment to evaluate the possibility of disseminating a time code via the SIRIO-1 satellite, by using the onboard VHF repeater is described. The precision in the synchronization of remote clocks was expected to be of the order of 0.1 to 1 ms. The RF carrier was in the VHF band, so that low cost receivers could be used and then a broader class of users could be served. An already existing repeater, even if not designed specifically for communications could be utilized; the operation of this repeater was not intended to affect any other function of the spacecraft (both the SHF repeater and the VHF telemetry link were active during the time code dissemination via the VHF transponder).

Detoma, E.↗