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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

Ensuring fault tolerance of phase-locked clocks

Processors within a real-time multiprocessor system must be synchronized with as little overhead as possible. Although synchronization can be achieved via both software (e.g., interactive convergence and interactive consistency algorithms) and hardware (e.g., multistage synchronizers and phase-locked clocks), phase-locked clocks are most attractive due to their small overheads. Despite the fact that synchronization of the multiprocessor system with phase-locked clocks is totally different in nature from the interactive consistency algorithm, it is presently proven that it must satisfy the same condition, N equal to or greater than 3m + 1, where N is the total number of clocks in the multiprocessor system and m is the maximum number of faults tolerable. Also presented are results showing how to design phase-locked clocks so as to be impervious up to a given arbitrary number of malicious failures.

Krishna, C. M.↗
NASA NTRS1993

Reliable interface design for combining asynchronous and synchronous circuits

In order to successfully integrate asynchronous and synchronous designs, great care must be taken at the interface between the two types of systems. Synchronizing asynchronous inputs with a free running clock can cause well-known problems with metastability in the synchronization circuits. Stretchable clocks allow a clock cycle to expand dynamically in response to the metastability effects of sampling asynchronous inputs. We use an interface organization where the special circuitry for detecting metastability and for stretching the clock that is delivered to the synchronous part of the system is encapsulated in a Q-flop-based interface. This provides a very convenient method for interfacing mixed systems, as the interface and clock generation circuitry are isolated into one special module, and neither the asynchronous nor the synchronous system need be modified internally to accommodate the interface. This is especially important when standard synchronous components are used as there is no opportunity to modify these parts. We show that this interface module is suitable for most mixed design needs and conclude with an example.

Josephson, Lueli↗
NASA NTRS2006

Comments on the "Byzantine Self-Stabilizing Pulse Synchronization" Protocol: Counter-examples

Embedded distributed systems have become an integral part of many safety-critical applications. There have been many attempts to solve the self-stabilization problem of clocks across a distributed system. An analysis of one such protocol called the Byzantine Self-Stabilizing Pulse Synchronization (BSS-Pulse-Synch) protocol from a paper entitled "Linear Time Byzantine Self-Stabilizing Clock Synchronization" by Daliot, et al., is presented in this report. This report also includes a discussion of the complexity and pitfalls of designing self-stabilizing protocols and provides counter-examples for the claims of the above protocol.

Malekpour, Mahyar R.↗
NASA NTRS1987

A rate-transparent, self-clocking line code

A reliable and economical new transmission code is presented with the following properties: zero dc content, baseband bandwidth conservation, self-clocking capability, and data-rate-transparent decoding and synchronization. Simple encoder/decoder and clock extractor circuits are given. The code is demonstrated in a wavelength-multiplexed fiber-optic communication system.

Prucnal, Paul R.↗
NASA NTRS1974

Method and apparatus for decoding compatible convolutional codes

This invention relates to learning decoders for decoding compatible convolutional codes. The decoder decodes signals which have been encoded by a convolutional coder and allows performance near the theoretical limit of performance for coded data systems. The decoder includes a sub-bit shift register wherein the received sub-bits are entered after regeneration and shifted in synchronization with a clock signal recovered from the received sub-bit stream. The received sub-bits are processed by a sub-bit decision circuit, entered into a sub-bit shift register, decoded by a decision circuit, entered into a data shift register, and updated to reduce data errors. The bit decision circuit utilizes stored sub-bits and stored data bits to determine subsequent data-bits. Data errors are reduced by using at least one up-date circuit.

Doland, G. D.↗
NASA NTRS1973

Instrumentation for one-way satellite PTTI applications

A review of general principles and operational procedures illustrates how the typical passive user and omni receiving antenna can recover Precise Time and Time Interval (PTTI) information from a low altitude navigation satellite system for clock calibration and synchronization. Detailed discussions of concepts and theory of the receiver design are presented. The importance of RF correlation of the received and local PN encoded sequences is emphasized as a means of reducing delay uncertainties of the instrumentation to values compatible with nanosecond to submicrosecond PTTI objectives. Two receiver configurations were fabricated for use in satellite-to-laboratory experiments. In one receiver the delay-locked loop for PN signals synchronization used a dithered amplitude detection process while the second receiver used a complex sums phase detection method for measurement of delay error. The necessity for compensation of Doppler shift is discussed. Differences in theoretical signal acquisition and tracking performance of the design concepts are noted.

Osborne, A. E.↗
NASA NTRS1982

Time code dissemination experiment via the SIRIO-1 VHF transponder

An experiment to evaluate the possibility of disseminating a time code via the SIRIO-1 satellite, by using the onboard VHF repeater is described. The precision in the synchronization of remote clocks was expected to be of the order of 0.1 to 1 ms. The RF carrier was in the VHF band, so that low cost receivers could be used and then a broader class of users could be served. An already existing repeater, even if not designed specifically for communications could be utilized; the operation of this repeater was not intended to affect any other function of the spacecraft (both the SHF repeater and the VHF telemetry link were active during the time code dissemination via the VHF transponder).

Detoma, E.↗
NASA NTRS1985

Synchronization for Optical PPM Signals

Method based on statistical properties of weak pulse-positionmodulated (PPM) signal enables synchronization of receiver clock with received-signal time base. Method applies to weak optical M-ary PPM signals, for which there is only one pulse of length Tp transmitted during one of timeslots of length T in each successive interval of M timeslots. Method requires small dead time, Td, at beginning and end of each timeslot, during which pulse amplitude is zero.

Vilnrotter, V. A.↗
NASA NTRS1989

Satellite range delay simulator for a matrix-switched time division multiple-access network simulator

The Systems Integration, Test, and Evaluation (SITE) facility at NASA Lewis Research Center is presently configured as a satellite-switched time division multiple access (SS-TDMA) network simulator. The purpose of SITE is to demonstrate and evaluate advanced communication satellite technologies, presently embodied by POC components developed under NASA contracts in addition to other hardware, such as ground terminals, designed and built in-house at NASA Lewis. Each ground terminal in a satellite communications system will experience a different aspect of the satellite's motion due mainly to daily tidal effects and station keeping, hence a different duration and rate of variation in the range delay. As a result of this and other effects such as local oscillator instability, each ground terminal must constantly adjust its transmit burst timing so that data bursts from separate ground terminals arrive at the satellite in their assigned time slots, preventing overlap and keeping the system in synchronism. On the receiving end, ground terminals must synchronize their local clocks using reference transmissions received through the satellite link. A feature of the SITE facility is its capability to simulate the varying propagation delays and associated Doppler frequency shifts that the ground terminals in the network have to cope with. Delay is achieved by means of two NASA Lewis designed and built range delay simulator (RDS) systems, each independently controlled locally with front panel switches or remotely by an experiment control and monitor (EC/M) computer.

Nagy, Lawrence A.↗
NASA NTRS1990

Satellite range delay simulator for a matrix-switched time division multiple-access network simulation system

The Systems Integration, Test, and Evaluation (SITE) facility at NASA Lewis Research Center is presently configured as a satellite-switched time division multiple access (SS-TDMA) network simulator. The purpose of SITE is to demonstrate and evaluate advanced communication satellite technologies, presently embodied by POC components developed under NASA contracts in addition to other hardware, such as ground terminals, designed and built in-house at NASA Lewis. Each ground terminal in a satellite communications system will experience a different aspect of the satellite's motion due mainly to daily tidal effects and station keeping, hence a different duration and rate of variation in the range delay. As a result of this and other effects such as local oscillator instability, each ground terminal must constantly adjust its transmit burst timing so that data bursts from separate ground terminals arrive at the satellite in their assigned time slots, preventing overlap and keeping the system in synchronism. On the receiving end, ground terminals must synchronize their local clocks using reference transmissions received through the satellite link. A feature of the SITE facility is its capability to simulate the varying propagation delays and associated Doppler frequency shifts that the ground terminals in the network have to cope with. Delay is ahcieved by means of two NASA Lewis designed and built range delay simulator (RDS) systems, each independently controlled locally with front panel switches or remotely by an experiment control and monitor (EC/M) computer.

Nagy, Lawrence A.↗
NASA NTRS1992

Control Circuit For Reed-Solomon Encoder

Control circuit designed for use with commercially available AHA4610 Reed-Solomon encoder. Needed to select depth of interleaving and to synchronize input and output blocks of data and parity bits with suitable clock signals. Circuit provides synchronizing and control signals for Reed-Solomon encoder. Encoder can operate with asynchronous input and output data streams at rates up to 80 Mb/s. Interleaving depth selectable, and accommodation to input data rate automatic.

Ross, Douglas↗
NASA NTRS2012

Time Distribution Using SpaceWire in the SCaN Testbed on ISS

A paper describes an approach for timekeeping and time transfer among the devices on the CoNNeCT project s SCaN Testbed. It also describes how the clocks may be synchronized with an external time reference; e.g., time tags from the International Space Station (ISS) or RF signals received by a radio (TDRSS time service or GPS). All the units have some sort of counter that is fed by an oscillator at some convenient frequency. The basic problem in timekeeping is relating the counter value to some external time standard such as UTC. With SpaceWire, there are two approaches possible: one is to just use SpaceWire to send a message, and use an external wire for the sync signal. This is much the same as with the RS- 232 messages and l pps line from a GPS receiver. However, SpaceWire has an additional capability that was added to make it easier - it can insert and receive a special "timecode" word in the data stream.

Lux, James P.↗
NASA NTRS2005

A Methodology for the Design and Verification of Globally Asynchronous/Locally Synchronous Architectures

Recent advanced in model-checking have made it practical to formally verify the correctness of many complex synchronous systems (i.e., systems driven by a single clock). However, many computer systems are implemented by asynchronously composing several synchronous components, where each component has its own clock and these clocks are not synchronized. Formal verification of such Globally Asynchronous/Locally Synchronous (GA/LS) architectures is a much more difficult task. In this report, we describe a methodology for developing and reasoning about such systems. This approach allows a developer to start from an ideal system specification and refine it along two axes. Along one axis, the system can be refined one component at a time towards an implementation. Along the other axis, the behavior of the system can be relaxed to produce a more cost effective but still acceptable solution. We illustrate this process by applying it to the synchronization logic of a Dual Fight Guidance System, evolving the system from an ideal case in which the components do not fail and communicate synchronously to one in which the components can fail and communicate asynchronously. For each step, we show how the system requirements have to change if the system is to be implemented and prove that each implementation meets the revised system requirements through modelchecking.

Miller, Steven P.↗
NASA NTRS1987

Synchronization tracking in pulse position modulation receiver

A clock pulse generator for decoding pulse position modulation in an optical communication receiver is synchronized by a delay tracking loop which multiplies impulses of a data pulse by the square wave clock pulses from the generator to produce positive impulses when the clock pulse is of one level, and negative impulses when the clock pulse is of another level. A delay tracking loop integrates the impulses and produces an error signal that adjusts the delay so the clock pulses will be synchronized with data pulses. A dead-time tau sub d is provided between data pulses of an interval tau sub p in the data pulse period tau. When synchronized, the average number of positive impulses integrated will equal the average number of negative impulses over the continuous stream of data pulses.

Vilnrotter, Victor A.↗
NASA NTRS2012

Gigabit Ethernet Asynchronous Clock Compensation FIFO

Clock compensation for Gigabit Ethernet is necessary because the clock recovered from the 1.25 Gb/s serial data stream has the potential to be 200 ppm slower or faster than the system clock. The serial data is converted to 10-bit parallel data at a 125 MHz rate on a clock recovered from the serial data stream. This recovered data needs to be processed by a system clock that is also running at a nominal rate of 125 MHz, but not synchronous to the recovered clock. To cross clock domains, an asynchronous FIFO (first-in-first-out) is used, with the write pointer (wprt) in the recovered clock domain and the read pointer (rptr) in the system clock domain. Because the clocks are generated from separate sources, there is potential for FIFO overflow or underflow. Clock compensation in Gigabit Ethernet is possible by taking advantage of the protocol data stream features. There are two distinct data streams that occur in Gigabit Ethernet where identical data is transmitted for a period of time. The first is configuration, which happens during auto-negotiation. The second is idle, which occurs at the end of auto-negotiation and between every packet. The identical data in the FIFO can be repeated by decrementing the read pointer, thus compensating for a FIFO that is draining too fast. The identical data in the FIFO can also be skipped by incrementing the read pointer, which compensates for a FIFO draining too slowly. The unique and novel features of this FIFO are that it works in both the idle stream and the configuration streams. The increment or decrement of the read pointer is different in the idle and compensation streams to preserve disparity. Another unique feature is that the read pointer to write pointer difference range changes between compensation and idle to minimize FIFO latency during packet transmission.

Duhachek, Jeff↗
NASA NTRS1984

Using GPS and VLBI technology to maintain 14 digit synchronization

To facilitate the navigation of spacecraft to the outer planets, Jupiter and beyond, the JPL-NASA Deep Space Network (DSN) has implemented three ensembles of atomic clocks at widely separated locations. These clocks must be maintained, synchronized, to with a few parts in 10 to the 13th power of each other and, the entire group must be maintained, to a lesser degree, in synchronism with Coordinated Universal Time (UTC)NBS/USNO. Over the last 1 1/2 years the DSN has been using Global Positioning Satellites (GPS) and Very Long Baseline Interferometry (VLBI) technology to perform these critical Frequency and Time (F&T) synchronization tasks. A year of F&T synchronization data collected from the intercomparison of 3 sets of cesium and hydrogen maser driven clock ensembles through the use of GPS and VLBI techniques are covered. Also covered, are some of the problems met and limitations of these two techniques at their present level of technology.

Ward, S. C.↗