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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS1975

A simulation analysis of phase processing circuitry in the Ohio University Omega receiver prototype

A FORTRAN IV simulation study of the all-digital phase-processing circuitry is described. A digital phase-lock loop (DPLL) forms the heart of the Omega navigation receiver prototype, and through the DPLL, the phase of the 10.2 KHz Omega signal was estimated when the true signal phase is contaminated with noise. The DPLL uses a frequency synthesizer as the reference oscillator. The synthesizer is composed of synchronous rate multipliers (SRM's) driven by a temperature-compensated crystal oscillator, and the use of the SRM's in this application introduces phase jitter which degrades system performance. Simulation of the frequency synthesizer discussed was to analyze the circuits on a bit-by-bit level in order to evaluate the overall design, to see easily the effects of proposed design changes prior to actual breadboarding, to determine the optimum integration time for the DPLL in an environment typical of general aviation conditions, and to quantify the phase error introduced by the SRM synthesizer and examine its effect on the system.

Palkovic, R. A.↗
NASA NTRS1984

Pipelined digital SAR azimuth correlator using hybrid FFT-transversal filter

A synthetic aperture radar system (SAR) having a range correlator is provided with a hybrid azimuth correlator which utilizes a block-pipe-lined fast Fourier transform (FFT). The correlator has a predetermined FFT transform size with delay elements for delaying SAR range correlated data so as to embed in the Fourier transform operation a corner-turning function as the range correlated SAR data is converted from the time domain to a frequency domain. The azimuth correlator is comprised of a transversal filter to receive the SAR data in the frequency domain, a generator for range migration compensation and azimuth reference functions, and an azimuth reference multiplier for correlation of the SAR data. Following the transversal filter is a block-pipelined inverse FFT used to restore azimuth correlated data in the frequency domain to the time domain for imaging.

Wu, C.↗
NASA NTRS1993

Frequency-Channelized Recovery Of Timing

Method of extracting bit or baud rate of excess bandwidth pulse-amplitude-modulated signal based on frequency-domain equivalent of time-domain delay-and-multiply operation. Involves use of outputs of Fourier-transform-based, channelized receiver. Very little priori knowledge of parameters of signal needed, and processing of signal by method yields spectral line at pulse-repetition rate.

Satorius, Edgar H.↗
NASA NTRS2011

On-Wafer S-Parameter Measurements in the 325-508-GHz Band

New circuits have been designed and fabricated with operating frequencies over 325 GHz. In order to measure S-parameters of these circuits, an extensive process of wafer dicing and packaging, and waveguide transition design, fabrication, and packaging would be required. This is a costly and time-consuming process before the circuit can be tested in waveguide. The new probes and calibration procedures will simplify the testing process. New on-wafer probes, and a procedure for their calibration, have been developed that allow fast and inexpensive S-parameter characterization of circuits in the 325 -508 -GHz frequency band. The on-wafer probes transition from rectangular waveguide to coplanar waveguide probe tips with 40- m nominal signal-to-ground pin pitch so as to allow for probing circuits on a wafer. The probes with bias tees have been optimized for minimal insertion loss and maximum return loss when placed on 50-ohm structures to allow for calibration. The calibration process has been developed using the Thru-Reflect-Line Agilent algorithm with JPL determined calibration structures and calibration coefficients for the algorithm. This new test capability is presently unique to JPL. With it, researchers will be able to better develop circuits such as low-noise amplifiers, power amplifiers, multipliers, and mixers for heterodyne receivers in the 325-508-GHz frequency band for remote sensing/spectroscopy.

Fung, King Man↗
NASA NTRS1991

Ultra-stable performance of the superconducting cavity maser

Recent measurements on the superconducting cavity maser (SCM) oscillator show frequency stability of parts in 10 exp 15 for times from 1 to 1000 sec. Phase noise of approximately -80 dB/f-cubed was also measured. This short- and mid-term performance is believed to be better than that of any known microwave oscillator. In particular, stability at a measuring time of 1 sec is 10 times better than that of a hydrogen maser, and phase noise at 8 GHz is more than 20 dB below that of the best multiplied quartz crystal oscillators. Substantial technical improvements have been made to eliminate frequency instability due to operational parameters. They are temperature, pump frequency, pump power, pump frequency polarization, temperature gradient, coupling strength, and output VSWR. Either the parameter was stabilized or the coefficient which couples the parameter to the operating frequency was minimized. A frequency pulling coil has been implemented and tested to enable the SCM to be slaved to a hydrogen maser with a time constant of approximately 50 sec. This combination would allow the excellent long term performance of the hydrogen maser to be improved by the newly available short term performance of the SCM.

Dick, G. J.↗
NASA NTRS1995

Simplified Digital Down-Converters

Design of digital frequency down-converters simplified by eliminating need for both high-speed number-controlled oscillators (NCOs) and mixer-multipliers, and implementing functions via multiplication coefficients of finite-impulse-response (FIR) filters. Simplification depends on particular choices of operating frequencies. Simplified designs implemented with commercial FIR integrated circuits.

Sigman, Elliott H.↗
NASA NTRS1976

CCD correlation techniques

Two CCD techniques were discussed for performing an N-point sampled data correlation between an input signal and an electronically programmable reference function. The design and experimental performance of an implementation of the direct time correlator utilizing two analog CCDs and MOS multipliers on a single IC were evaluated. The performance of a CCD implementation of the chirp z transform was described, and the design of a new CCD integrated circuit for performing correlation by multiplication in the frequency domain was presented. This chip provides a discrete Fourier transform (DFT) or inverse DFT, multipliers, and complete support circuitry for the CCD CZT. The two correlation techniques are compared.

Hewes, C. R.↗
NASA NTRS1994

Analysis of DE-1 PWI electric field data

The measurement of low frequency electric field oscillations may be accomplished with the Plasma Wave Instrument (PWI) on DE 1. Oscillations at a frequency around 1 Hz are below the range of the conventional plasma wave receivers, but they can be detected by using a special processing of the quasi-static electric field data. With this processing it is also possible to determine if the electric field oscillations are predominately parallel or perpendicular to the ambient magnetic field. The quasi-static electric field in the DE 1 spin/orbit plane is measured with a long-wire 'double probe'. This antenna is perpendicular to the satellite spin axis, which in turn is approximately perpendicular to the geomagnetic field in the polar magnetosphere. The electric field data are digitally sampled at a frequency of 16 Hz. The measured electric field signal, which has had phase reversals introduced by the rotating antenna, is multiplied by the sine of the rotation angle between the antenna and the magnetic field. This is called the 'perpendicular' signal. The measured time series is also multiplied with the cosine of the angle to produce a separate 'parallel' signal. These two separate time series are then processed to determine the frequency power spectrum.

Weimer, Daniel↗
NASA NTRS2008

Digital Receiver Phase Meter

The software of a commercially available digital radio receiver has been modified to make the receiver function as a two-channel low-noise phase meter. This phase meter is a prototype in the continuing development of a phase meter for a system in which radiofrequency (RF) signals in the two channels would be outputs of a spaceborne heterodyne laser interferometer for detecting gravitational waves. The frequencies of the signals could include a common Doppler-shift component of as much as 15 MHz. The phase meter is required to measure the relative phases of the signals in the two channels at a sampling rate of 10 Hz at a root power spectral density <5 microcycle/(Hz)1/2 and to be capable of determining the power spectral density of the phase difference over the frequency range from 1 mHz to 1 Hz. Such a phase meter could also be used on Earth to perform similar measurements in laser metrology of moving bodies. To illustrate part of the principle of operation of the phase meter, the figure includes a simplified block diagram of a basic singlechannel digital receiver. The input RF signal is first fed to the input terminal of an analog-to-digital converter (ADC). To prevent aliasing errors in the ADC, the sampling rate must be at least twice the input signal frequency. The sampling rate of the ADC is governed by a sampling clock, which also drives a digital local oscillator (DLO), which is a direct digital frequency synthesizer. The DLO produces samples of sine and cosine signals at a programmed tuning frequency. The sine and cosine samples are mixed with (that is, multiplied by) the samples from the ADC, then low-pass filtered to obtain in-phase (I) and quadrature (Q) signal components. A digital signal processor (DSP) computes the ratio between the Q and I components, computes the phase of the RF signal (relative to that of the DLO signal) as the arctangent of this ratio, and then averages successive such phase values over a time interval specified by the user.

Marcin, Martin↗
NASA NTRS2010

SEE Tolerant Self-Calibrating Simple Fractional-N PLL

We show a reliable on-chip clock multiplier for SEE testing or RHBD applications. Fine control of clock frequency is provided without complex delta-sigma schemes. Conflicts that can occur with voted PLLs are discussed, and how to avoid them.

Shuler, Robert L.↗
NASA NTRS2016

THz Limb Sounder (TLS) for Lower Thermospheric Wind, Oxygen Density, and Temperature

Neutral winds are one of the most critical measurements in the lower thermosphere and E region ionosphere (LTEI) for understanding complex electrodynamic processes and ion-neutral interactions. We are developing a high-sensitivity, low-power, noncryogenic 2.06 THz Schottky receiver to measure wind profiles at 100-140 km. The new technique, THz limb sounder (TLS), aims to measure LTEI winds by resolving the wind-induced Doppler shift of 2.06 THz atomic oxygen (OI) emissions. As a transition between fine structure levels in the ground electronic state, the OI emission is in local thermodynamic equilibrium(LTE) at altitudes up to 350km. This LTE property, together with day-and-night capability and small line-of-sight gradient, makes the OI limb sounding a very attractive technique for neutral wind observations. In addition to the wind measurement, TLS can also retrieve [OI] density and neutral temperature in the LTEI region. TLS leverages rapid advances in THz receiver technologies including subharmonically pumped (SHP)mixers and Schottky-diode-based power multipliers. Current SHP Schottky receivers have produced good sensitivity for THz frequencies at ambient environment temperatures (120-150 K), which are achievable through passively cooling in spaceflight. As an emerging technique, TLS can fill the critical data gaps in the LTEI neutral wind observations to enable detailed studies on the coupling and dynamo processes between charged and neutral molecules.

wind profiles↗
NASA NTRS1978

Lightweight multiple output converter development

A high frequency, multiple output power conditioner was developed and breadboarded using an eight-stage capacitor diode voltage multiplier to provide +1200 Vdc, and a three-stage for -350 Vdc. In addition, two rectifier bridges were capacitively coupled to the eight-stage multiplier to obtain 0.5 and 0.65 a dc constant current outputs referenced to +1200 Vdc. Total power was 120 watts, with an overall efficiency of 85 percent at the 80 kHz operating frequency. All outputs were regulated to three percent or better, with complete short circuit protection. The power conditioner component weight and efficiency were compared to the equivalent four outputs of the 10 kHz conditioner for the 8 cm ion engine. Weight reduction for the four outputs was 557 grams; extrapolated in the same ratio to all nine outputs, it would be 1100 to 1400 grams.

Kisch, J. J.↗
NASA NTRS2014

All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Shuler, Robert L., Jr.↗
NASA NTRS2014

ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Schuler, Robert L., Jr.↗
NASA NTRS1972

Time-domain technique for optimal design of digital-filter equalizers.

A technique is presented for the design of frequency-sampling and transversal digital filters from specified unit-impulse responses. The multiplier coefficients for the digital filter are specified by the use of a linear-programming algorithm. Examples include the design of digital filters to generate intersymbol-free pulses for data transmission over ideal bandlimited channels and to equalize data transmission channels that have known unit-impulse responses.

Burlage, D. W.↗
NASA NTRS1983

Measuring Power Flow in Electric Vehicles

Instrument accommodates fast rise and fall times of waveforms characteristic of modern, efficient power controllers. Power meter multiplies analog signals proportional to voltage and current, and converts resulting signal to frequency. Two mechanical counters provided: one for charging, one for discharging.

Griffin, Daniel C., Jr↗
NASA NTRS1974

High performance dc-dc conversion with voltage multipliers

An experimental 100W 1000V dc-dc converter using a capacitor diode voltage multipler (CDVM) with a nominal frequency of 100 kHz is studied. A component weight of about 1 kg/kW was obtained. Design equations for current, output -ripple and -power, efficiency and output voltage are derived. Agreement between experimental results and calculations is fairly good except for ripple.

Harrigill, W. T., Jr.↗