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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 217 records · Page 12
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Compact, Low-Overhead, MIL-STD-1553B Controller

A compact and flexible controller has been developed to provide MIL-STD- 1553B Remote Terminal (RT) communications and supporting and related functions with minimal demand on the resources of the system in which the controller is to be installed. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD-1553B is commonly used in defense and space applications.) Many other MIL-STD-1553B RT controllers are complicated, and to enable them to function, it is necessary to provide software and to use such ancillary separate hardware devices as microprocessors and dual-port memories. The present controller functions without need for software and any ancillary hardware. In addition, it contains a flexible system interface and extensive support hardware while including on-chip error-checking and diagnostic support circuitry. This controller is implemented within part of a modern field-programmable gate array.

Katz, Richard↗
NASA NTRS2009

Low-Noise MMIC Amplifiers for 120 to 180 GHz

Three-stage monolithic millimeter-wave integrated-circuit (MMIC) amplifiers capable of providing useful amounts of gain over the frequency range from 120 to 180 GHz have been developed as prototype low-noise amplifiers (LNAs) to be incorporated into instruments for sensing cosmic microwave background radiation. There are also potential uses for such LNAs in electronic test equipment, passive millimeter- wave imaging systems, radar receivers, communication receivers, and systems for detecting hidden weapons. The main advantage afforded by these MMIC LNAs, relative to prior MMIC LNAs, is that their coverage of the 120-to-180-GHz frequency band makes them suitable for reuse in a wider variety of applications without need to redesign them. Each of these MMIC amplifiers includes InP transistors and coplanar waveguide circuitry on a 50- mthick chip (see Figure 1). Coplanar waveguide transmission lines are used for both applying DC bias and matching of input and output impedances of each transistor stage. Via holes are incorporated between top and bottom ground planes to suppress propagation of electromagnetic modes in the substrate. On the basis of computational simulations, each of these amplifiers was expected to operate with a small-signal gain of 14 dB and a noise figure of 4.3 dB. At the time of writing this article, measurements of noise figures had not been reported, but on-chip measurements had shown gains approaching their simulated values (see Figure 2).

Pukala, David↗
NASA NTRS2007

NASA Tech Briefs, June 2007

Topics covered include: High-Accuracy, High-Dynamic-Range Phase-Measurement System; Simple, Compact, Safe Impact Tester; Multi-Antenna Radar Systems for Doppler Rain Measurements; 600-GHz Electronically Tunable Vector Measurement System; Modular Architecture for the Measurement of Space Radiation; VLSI Design of a Turbo Decoder; Architecture of an Autonomous Radio Receiver; Improved On-Chip Measurement of Delay in an FPGA or ASIC; Resource Selection and Ranking; Accident/Mishap Investigation System; Simplified Identification of mRNA or DNA in Whole Cells; Printed Multi-Turn Loop Antennas for RF Biotelemetry; Making Ternary Quantum Dots From Single-Source Precursors; Improved Single-Source Precursors for Solar-Cell Absorbers; Spray CVD for Making Solar-Cell Absorber Layers; Glass/BNNT Composite for Sealing Solid Oxide Fuel Cells; A Method of Assembling Compact Coherent Fiber-Optic Bundles; Manufacturing Diamond Under Very High Pressure; Ring-Resonator/Sol-Gel Interferometric Immunosensor; Compact Fuel-Cell System Would Consume Neat Methanol; Algorithm Would Enable Robots to Solve Problems Creatively; Hypothetical Scenario Generator for Fault-Tolerant Diagnosis; Smart Data Node in the Sky; Pseudo-Waypoint Guidance for Proximity Spacecraft Maneuvers; Update on Controlling Herds of Cooperative Robots; and Simulation and Testing of Maneuvering of a Planetary Rover.

Source record↗
NASA NTRS2010

Biasable, Balanced, Fundamental Submillimeter Monolithic Membrane Mixer

This device is a biasable, submillimeter-wave, balanced mixer fabricated using JPL s monolithic membrane process a simplified version of planar membrane technology. The primary target application is instrumentation used for analysis of atmospheric constituents, pressure, temperature, winds, and other physical and chemical properties of the atmospheres of planets and comets. Other applications include high-sensitivity gas detection and analysis. This innovation uses a balanced configuration of two diodes allowing the radio frequency (RF) signal and local oscillator (LO) inputs to be separated. This removes the need for external diplexers that are inherently narrowband, bulky, and require mechanical tuning to change frequency. Additionally, this mixer uses DC bias-ability to improve its performance and versatility. In order to solve problems relating to circuit size, the GaAs membrane process was created. As much of the circuitry as possible is fabricated on-chip, making the circuit monolithic. The remainder of the circuitry is precision-machined into a waveguide block that holds the GaAs circuit. The most critical alignments are performed using micron-scale semiconductor technology, enabling wide bandwidth and high operating frequencies. The balanced mixer gets superior performance with less than 2 mW of LO power. This can be provided by a simple two-stage multiplier chain following an amplifier at around 90 GHz. Further, the diodes are arranged so that they can be biased. Biasing pushes the diodes closer to their switching voltage, so that less LO power is required to switch the diodes on and off. In the photo, the diodes are at the right end of the circuit. The LO comes from the waveguide at the right into a reduced-height section containing the diodes. Because the diodes are in series to the LO signal, they are both turned on and off simultaneously once per LO cycle. Conversely, the RF signal is picked up from the RF waveguide by the probe at the left, and flows rightward to the diodes. Because the RF is in a quasi- TEM (suspended, microstrip-like) mode, it impinges on the diodes in an anti-parallel mode that does not couple to the waveguide mode. This isolates the LO and RF signals. This operation is similar to a cross-bar mixer used at low frequencies, except the RF signal enters through the back-short end of the waveguide rather than through the side. The RF probe also conveys the down-converted intermediate frequency (IF) signal out to an off-chip circuit board through a simple LC low-pass filter to the left as indicated. The bias is brought to the diodes through a bypass capacitor at the top.

Siegel, Peter↗
NASA NTRS1995

Application of New Technology to Future Celestial Trackers

New developments in image sensors and optical materials have opened the door to dramatic mass and power reductions in celestial tracker designs. The rapid development of active pixel sensors (APS) has provided a new detector choice offering high on-chip integration of support circuitry at reduced power consumption. Silicon-Carbide (Si-C) optics are one of the new developments in low-mass optical components. We describe the celestial tracker needs of an Autonomous Feature and Star Tracking (AFAST) system designed for autonomous spacecraft control. Details of a low mass celestial tracker, based on a low power APS array and optimized for an AFAST system, are discussed.

active↗
NASA NTRS1996

Programmable Multiresolution CMOS Active Pixel Sensor

CMOS active pixel sensors (APS) allow the flexibility of placing signal processing circuitry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off-chip software intensive image processing. This 128 x 128 APS array can be read out at any user-defined resolution by configuring a set of digital shift registers. The resolution frame rate is 30 Hz with higher rates for all other image resolutions.

APS↗
NASA NTRS1993

Application of the Active Pixel Sensor Concept to Guidance and Navigation

Charge-coupled devices (CCDs) have been used extensively in the past in star trackers and fine guidance systems. A new technology, the active pixel sensor, is a possible successor to CCDs. This technology potentially features the same sensitivity and performance of the CCD with additional improvements. These improvements include random access capability, easy window-of-interest readout, non-destructive readout for signal-to-noise improvement, high radiation tolerance, simplified clocking voltages, and easy integration with other on-chip signal processing circuitry. The state-of-the-art of this emerging technology and its potential application to guidance and navigation systems is discussed.

Eisenman, Allan R.↗
NASA NTRS1996

256X256 CMOS Active Pixel Sensor Camera-on-a-Chip

A CMOS imaging sensor is described that uses active pixel sensor (APS) technology which permits the integration of the detector array with on-chip timing, control and signal chain electronics. This sensor has been used to implement a CMOS APS camera-on-a-chip.

active↗
DOE OSTI2025

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems

Domain-specific systems improve the performance of a specific set of applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration to optimize the compute performance of the generated accelerators. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how the accelerators access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.

Limaye, Ankur M. (ORCID:0000000194062584)↗
DOE OSTI2025

Design and Performance of the SPT-SLIM Receiver Cryostat

The South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM) is a millimeter-wavelength line-intensity mapping experiment, which was deployed on the South Pole Telescope (SPT) during the 2024-2025 Austral summer season. This pathfinder experiment serves to demonstrate the on-sky operation of multi-pixel on-chip spectrometer technology. We report on the cryogenic performance of the SPT-SLIM receiver for the first year of commissioning observations. The SPT-SLIM receiver utilizes an Adiabatic Demagnetization Refrigerator (ADR) for cooling the focal plane of superconducting filterbank spectrometers to a temperature of 150 mK. We demonstrate stable thermal performance of the focal plane module during observations consistent with thermal modeling, enabling a cryogenic operating efficiency above 80%. We also report on the receiver control system design utilizing the Observatory Control System (OCS) platform for automated cryogenic operation on the SPT.

Young, M. R. [Fermilab; Chicago U., KICP]↗
DOE OSTI2025

An On-Sky Atmospheric Calibration of SPT-SLIM

We present the methodology and results of the on-sky responsivity calibration of the South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM). SPT-SLIM is a pathfinder line intensity mapping experiment utilizing the on-chip spectrometer technology, and was first deployed during the 2024-2025 Austral Summer season on the South Pole Telescope. During the two-week on-sky operation of SPT-SLIM, we performed periodic measurements of the detector response as a function of the telescope elevation angle. Combining these data with atmospheric opacity measurements from an on-site atmospheric tipping radiometer, simulated South Pole atmospheric spectra, and measured detector spectral responses, we construct estimates for the responsivity of SPT-SLIM detectors to sky loading. We then use this model to calibrate observations of the moon taken by SPT-SLIM, cross-checking the result against the known brightness temperature of the Moon as a function of its phase.

Dibert, K. R. [Chicago U., Astron. Astrophys. Ctr.↗
DOE OSTI2025

Obsidian

Obsidian A35 is a compact FPGA carrier board designed to interface with ADCs, DACs or other devices, either stand-alone or as an I/O expansion board. The connectivity includes 1 GigE, 4 SFP, 6 PMOD, FTDI USB and Arduino shield compatible header. The board features also a FPGA boot SPI Flash, on-chip DDR3 memory, VCXO and White Rabbit compatibility.

Moore, Victoria [Lawrence Berkeley National Labora↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗
DOE OSTI2026

A 3D-Printed Millimeter-Wave Inline Waveguide-to-Coplanar-Waveguide Transition to Enable Dense Spectrometer Arrays for Intensity Mapping Surveys

We present a 3D-printed millimeter-wave, octave-bandwidth, in-line waveguide-to-coplanar-waveguide transition designed to enable focal planes with dense arrays of on-chip spectrometers. These arrays will enable compelling surveys of the large-scale structure of the universe through millimeter-wave intensity mapping. The transition consists of a four-step ridge-waveguide transformer that couples light from a rectangular waveguide onto a coplanar waveguide via an electrical connection made with indium bump bonds. We develop a tolerance-aware optimization approach to identify high-performance transition geometries that are robust to manufacturing variations; the same formulation can be applied to other tolerance-sensitive design problems. We also describe the implementation of a custom apparatus and procedure for bump-bonding a silicon chip to a metallized 3D-printed component. We detail the fabrication of the coplanar waveguide chip and three-dimensional waveguide structure, simulations and metrology of a test device, and room temperature reflectance measurements of this device. The room temperature metrology and reflection measurements are consistent with a model that predicts a coupling efficiency of $\mathord{\sim} 95\%$ at cryogenic temperatures in the 85-170 GHz frequency range.

Stover, Austin [Chicago U.; Chicago U., KICP] (ORC↗
NASA NTRS2003

Switch array system for thin film lithium microbatteries

This paper presents a design approach for charging and discharging microbatteries. Maximum flexibility in terms of voltages and currents are also obtained through the use of a switching matrix.

microbattery on-chip power micropower↗