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All sourcesNASA NTRSDOE OSTI
NASA NTRS2014

Avionics Architectures for Exploration: Ongoing Efforts in Human Spaceflight

The field of Avionics is advancing far more rapidly in terrestrial applications than in spaceflight applications. Spaceflight Avionics are not keeping pace with expectations set by terrestrial experience, nor are they keeping pace with the need for increasingly complex automation and crew interfaces as we move beyond Low Earth Orbit. NASA must take advantage of the strides being made by both space-related and terrestrial industries to drive our development and sustaining costs down. This paper describes ongoing efforts by the Avionics Architectures for Exploration (AAE) project chartered by NASA's Advanced Exploration Systems (AES) Program to evaluate new avionic architectures and technologies, provide objective comparisons of them, and mature selected technologies for flight and for use by other AES projects. The AAE project team includes members from most NASA centers, and from industry. It is our intent to develop a common core avionic system that has standard capabilities and interfaces, and contains the basic elements and functionality needed for any spacecraft. This common core will be scalable and tailored to specific missions. It will incorporate hardware and software from multiple vendors, and be upgradeable in order to infuse incremental capabilities and new technologies. It will maximize the use of reconfigurable open source software (e.g., Goddard Space Flight Center's (GSFC's) Core Flight Software (CFS)). Our long-term focus is on improving functionality, reliability, and autonomy, while reducing size, weight, and power. Where possible, we will leverage terrestrial commercial capabilities to drive down development and sustaining costs. We will select promising technologies for evaluation, compare them in an objective manner, and mature them to be available for future programs. The remainder of this paper describes our approach, technical areas of emphasis, integrated test experience and results as of mid-2014, and future plans. As a part of the AES Program, we are encouraged to set aggressive goals and fall short if necessary, rather than to set our sights too low. We are also asked to emphasize providing our personnel with hands-on experience in development, integration, and testing. That we have embraced both of these philosophies will be evident in the descriptions below.

Goforth, Montgomery B.↗
NASA NTRS1980

A polymorphic reconfigurable emulator for parallel simulation

Microprocessor and arithmetic support chip technology was applied to the design of a reconfigurable emulator for real time flight simulation. The system developed consists of master control system to perform all man machine interactions and to configure the hardware to emulate a given aircraft, and numerous slave compute modules (SCM) which comprise the parallel computational units. It is shown that all parts of the state equations can be worked on simultaneously but that the algebraic equations cannot (unless they are slowly varying). Attempts to obtain algorithms that will allow parellel updates are reported. The word length and step size to be used in the SCM's is determined and the architecture of the hardware and software is described.

Parrish, E. A., Jr.↗
NASA NTRS2004

SCA Waveform Development for Space Telemetry

The NASA Glenn Research Center is investigating and developing suitable reconfigurable radio architectures for future NASA missions. This effort is examining software-based open-architectures for space based transceivers, as well as common hardware platform architectures. The Joint Tactical Radio System's (JTRS) Software Communications Architecture (SCA) is a candidate for the software approach, but may need modifications or adaptations for use in space. An in-house SCA compliant waveform development focuses on increasing understanding of software defined radio architectures and more specifically the JTRS SCA. Space requirements put a premium on size, mass, and power. This waveform development effort is key to evaluating tradeoffs with the SCA for space applications. Existing NASA telemetry links, as well as Space Exploration Initiative scenarios, are the basis for defining the waveform requirements. Modeling and simulations are being developed to determine signal processing requirements associated with a waveform and a mission-specific computational burden. Implementation of the waveform on a laboratory software defined radio platform is proceeding in an iterative fashion. Parallel top-down and bottom-up design approaches are employed.

Mortensen, Dale J.↗
NASA NTRS2012

Dynamically Reconfigurable Systolic Array Accelerator

A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems. FPGA chips can be responsive to realtime demands for changing applications needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

Dasu, Aravind↗
NASA NTRSDate not supplied

Hardware Autonomy for Space Infrastructure

NASA prioritizes autonomous systems development with the expectation that it will continue to drive significant improvements in human and science exploration capability. Crew operations benefit from a spectrum of machine assistance to complete replacement of dangerous or highly repetitive tasks. Many science operations have a teleoperation component, and similarly benefit from a range of autonomy implementations that make long distance applications feasible. As we consider longer duration deep space missions, we also consider higher levels of autonomy in order meet emergent safety, maintenance, and logistics needs. One of the challenges within this scope is installation and maintenance of infrastructure, such as large scale instrumentation and communications equipment, crew habitats, and operational facilities. We describe how a programmable meta-material architecture may shift the paradigm of how we design, build, and operate future space infrastructure and assets. A primary objective of this strategy is to free the design space from launch vehicle constraints and fundamentally shift how a mission is designed and conducted. This integrates advances in materials (mechanical meta-materials), manufacturing (cooperative mobile robotics), and autonomy (multi-agent planning algorithms). Engineering systems that utilize a modular and reconfiguration building block approach, such as digital communication and computation systems, currently lead in terms of size and complexity scalability. NASA is extending the benefits and flexibility of digital systems to hardware systems, to optimize materials life-cycle management and expand our space exploration mission capabilities to meet long duration and deep space infrastructure needs, in accordance with long term NASA goals of "in-space reliance" and "mass-less exploration."

In space assembly↗
NASA NTRS1980

Design of a modular digital computer system

A Central Control Element (CCE) module which controls the Automatically Reconfigurable Modular System (ARMS) and allows both redundant processing and multi-computing in the same computer with real time mode switching, is discussed. The same hardware is used for either reliability enhancement, speed enhancement, or for a combination of both.

Source record↗
NASA NTRS1990

Advanced telemetry systems for payloads. Technology needs, objectives and issues

The current trends in advanced payload telemetry are the new developments in advanced modulation/coding, the applications of intelligent techniques, data distribution processing, and advanced signal processing methodologies. Concerted efforts will be required to design ultra-reliable man-rated software to cope with these applications. The intelligence embedded and distributed throughout various segments of the telemetry system will need to be overridden by an operator in case of life-threatening situations, making it a real-time integration issue. Suitable MIL standards on physical interfaces and protocols will be adopted to suit the payload telemetry system. New technologies and techniques will be developed for fast retrieval of mass data. Currently, these technology issues are being addressed to provide more efficient, reliable, and reconfigurable systems. There is a need, however, to change the operation culture. The current role of NASA as a leader in developing all the new innovative hardware should be altered to save both time and money. We should use all the available hardware/software developed by the industry and use the existing standards rather than inventing our own.

Source record↗
NASA NTRS2017

Programmable Logic Device (PLD) Design Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. At the conclusion of the development, the software and hardware description language (HDL) code was delivered to JSC for their use in their iPAS test bed to get hands-on experience with the STRS standard, and for development of their own STRS Waveforms on the now STRS compliant platform.The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe the design of the HDL code for the FPGA portion of the iPAS STRS Radio particularly the design of the FPGA wrapper and the test waveform.

VHDL↗
NASA NTRS2007

More About Software for No-Loss Computing

A document presents some additional information on the subject matter of "Integrated Hardware and Software for No- Loss Computing" (NPO-42554), which appears elsewhere in this issue of NASA Tech Briefs. To recapitulate: The hardware and software designs of a developmental parallel computing system are integrated to effectuate a concept of no-loss computing (NLC). The system is designed to reconfigure an application program such that it can be monitored in real time and further reconfigured to continue a computation in the event of failure of one of the computers. The design provides for (1) a distributed class of NLC computation agents, denoted introspection agents, that effects hierarchical detection of anomalies; (2) enhancement of the compiler of the parallel computing system to cause generation of state vectors that can be used to continue a computation in the event of a failure; and (3) activation of a recovery component when an anomaly is detected.

Edmonds, Iarina↗
NASA NTRS2011

Enabling Future Robotic Missions with Multicore Processors

Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

multi-core processor↗
NASA NTRSDate not supplied

Development of a Thermal Vacuum Chamber for Lunar Surface Simulation

Simulating the lunar surface environment is a critical component in advancing the Technology Readiness Level (TRL) of newly developed lunar surface exploration systems and understanding regolith dynamics. Developing systems with the ability to simulate the lunar surface environment presents unique challenges associated with both the hardware requirements of the system and the uniqueness of the lunar environment. Additionally, many thermal vacuum testing systems are large and expensive to maintain and operate, increasing the cost for the end users. Many low TRL prototypes are small-scale and low-cost, making it unfeasible and unnecessary to utilize larger scale testing facilities. A small-scale, modular, and easily reconfigurable chamber with a quick testing turnaround time could allow rapid TRL advancement with minimal costs and time commitments relative to many of the current testing facilities. Here, we introduce a thermal vacuum chamber system that will support experimentation and rapid testing and maturation of small-scale hardware systems and subsystems for lunar surface exploration.

Thermal Vacuum Chamber↗
NASA NTRS1984

Design and evaluation of a fault-tolerant multiprocessor using hardware recovery blocks

Attention is given to the design and evaluation of a fault-tolerant multiprocessor whose rollback recovery mechanism is based on hardware recovery blocks constructed by consecutive state-save operations and several state-save units in every processor and memory module. Upon detection of failure, the multiprocessor reconfigures itself to replace the faulty module and the process originally assigned to the faulty module retreats to one of the previously saved states, in order to resume fault-free execution. A mathematical model is proposed for the calculation of multistep rollback recovery coverage and the risk of restart when all available saved states are exhausted. The mean and the variance of task execution time with the occurrence of rollbacks and/or restarts are evaluated.

Lee, Y.-H.↗
NASA NTRS2014

Innovation in Deep Space Habitat Interior Design: Lessons Learned From Small Space Design in Terrestrial Architecture

Increased public awareness of carbon footprints, crowding in urban areas, and rising housing costs have spawned a 'small house movement' in the housing industry. Members of this movement desire small, yet highly functional residences which are both affordable and sensitive to consumer comfort standards. In order to create comfortable, minimum-volume interiors, recent advances have been made in furniture design and approaches to interior layout that improve both space utilization and encourage multi-functional design for small homes, apartments, naval, and recreational vehicles. Design efforts in this evolving niche of terrestrial architecture can provide useful insights leading to innovation and efficiency in the design of space habitats for future human space exploration missions. This paper highlights many of the cross-cutting architectural solutions used in small space design which are applicable to the spacecraft interior design problem. Specific solutions discussed include reconfigurable, multi-purpose spaces; collapsible or transformable furniture; multi-purpose accommodations; efficient, space saving appliances; stowable and mobile workstations; and the miniaturization of electronics and computing hardware. For each of these design features, descriptions of how they save interior volume or mitigate other small space issues such as confinement stress or crowding are discussed. Finally, recommendations are provided to provide guidance for future designs and identify potential collaborations with the small spaces design community.

Simon, Matthew A.↗
NASA NTRS1974

Modular digital computer system design

Automatically-Reconfigurable Modular Multiprocessor System (ARMMS) provides redundant processing with dynamic mode switching in real time. Design will provide higher computer capability than that presently available for same amount of hardware and will furnish modular system which is responsive to diverse problems effectively.

Source record↗
NASA NTRS1987

Programming methodology for a general purpose automation controller

The General Purpose Automation Controller is a multi-processor architecture for automation programming. A methodology has been developed whose aim is to simplify the task of programming distributed real-time systems for users in research or manufacturing. Programs are built by configuring function blocks (low-level computations) into processes using data flow principles. These processes are activated through the verb mechanism. Verbs are divided into two classes: those which support devices, such as robot joint servos, and those which perform actions on devices, such as motion control. This programming methodology was developed in order to achieve the following goals: (1) specifications for real-time programs which are to a high degree independent of hardware considerations such as processor, bus, and interconnect technology; (2) a component approach to software, so that software required to support new devices and technologies can be integrated by reconfiguring existing building blocks; (3) resistance to error and ease of debugging; and (4) a powerful command language interface.

Sturzenbecker, M. C.↗
NASA NTRS2006

Design and Testing of Space Telemetry SCA Waveform

A Software Communications Architecture (SCA) Waveform for space telemetry is being developed at the NASA Glenn Research Center (GRC). The space telemetry waveform is implemented in a laboratory testbed consisting of general purpose processors, field programmable gate arrays (FPGAs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). The radio hardware is integrated with an SCA Core Framework and other software development tools. The waveform design is described from both the bottom-up signal processing and top-down software component perspectives. Simulations and model-based design techniques used for signal processing subsystems are presented. Testing with legacy hardware-based modems verifies proper design implementation and dynamic waveform operations. The waveform development is part of an effort by NASA to define an open architecture for space based reconfigurable transceivers. Use of the SCA as a reference has increased understanding of software defined radio architectures. However, since space requirements put a premium on size, mass, and power, the SCA may be impractical for today s space ready technology. Specific requirements for an SCA waveform and other lessons learned from this development are discussed.

Mortensen, Dale J.↗
NASA NTRS1993

Embeddable Reconfigurable Neuroprocessors

Reconfigurable and cascadable building block neural network chips, fabricated using analog VLSI design tools, are interfaced to a PC. The building block chip designs, the cascadability and the hardware-in-the-loop supervised learning aspects of these chips are described.

Neuroprocessors↗