Reliability of imperfect redundant systems
Reliability estimation of redundant systems for determining statistical probability of mission success
STATISTICAL PROBABILITY↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Redundancy techniques to improve the reliability of two level and three level logic circuits
Redundancy techniques in two and three level logic circuits - reliability improvement
CIRCUIT RELIABILITY↗
Research and investigative analysis using Kron's method of analyzing redundant structures
Response characteristics, frequency, and mode shape of Saturn SA-DI vehicle - analysis of redundant structures
MODE SHAPE↗
A redundant low power PCM telemeter for the orbiting solar observatory
Redundant low power PCM telemeter for OSO
OSO↗
A redundant spacecraft sequencer breadboard Phase I report, Dec. 22, 1965 - Mar. 30, 1966
Combined integrated and discrete circuit breadboard model for redundant multiple logic version of Mariner C spacecraft central computer and sequencer
REDUNDANT SYSTEM↗
Circuits and circuit testing for spaceborne redundant digital systems Special technical report no. 3
Design and testing of majority logic redundancy for spaceborne and GSE digital systems
REDUNDANT SYSTEM↗
A study of high-speed AD and DA converters using redundancy techniques Interim report, May 10, 1963 - May 9, 1964
High speed analog-to-digital converters compared using redundancy encoding techniques
ANALOG-TO-DIGITAL CONVERTER↗
Compendium of redundancy removal processes.
Redundancy removal processes, classification and nomenclature compared by plotting compression ratio vs rms error and stressing ZVA process
RANDOM SIGNAL↗
Redundant spacecraft sequencer breadboard Final report, 30 Mar. - 30 Jun. 1966
Circuitry, logical design, and test data on redundant spacecraft sequencer breadboard
MARINER C PROGRAM↗
Reliabilities of redundant electrical generator systems
Reliability of redundant electrical generating system configurations for use in SNAP-2 AND SNAP-8
REDUNDANT STRUCTURE↗
Eliminating redundancy in fixed frame television
Eliminating redundancy in fixed frame television, and relationship between spectral properties of original sampled waveform and interpolation error
SAMPLED DATA↗
Application of redundancy study, volume 4 Final report
Redundancy at both mission and spacecraft systems level of Voyager program
VOYAGER PROJECT↗
Partial versus total redundancy.
Partial redundancy for improved reliability of computing machine
CIRCUIT RELIABILITY↗
Redundant system test point allocation and mission reliability estimation procedures.
Optimal allocation of n test points within redundant digital system for prelaunch and in-flight spacecraft reliability estimate
DIGITAL TECHNIQUE↗
Application of redundancy in the Saturn V guidance and control system.
Application of redundancy in Saturn V guidance and control system to achieve desired reliability
SATURN V LAUNCH VEHICLE↗
Effective guidance and control redundancy.
Effective guidance and control redundancy for spacecraft configurations and mission outcomes, discussing computer systems
REDUNDANT SYSTEM↗
Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays
We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.
error rate calculations↗
Verification of Triple Modular Redundancy (TMR) Insertion for Reliable and Trusted Systems
We propose a method for TMR insertion verification that satisfies the process for reliable and trusted systems. If a system is expected to be protected using TMR, improper insertion can jeopardize the reliability and security of the system. Due to the complexity of the verification process, there are currently no available techniques that can provide complete and reliable confirmation of TMR insertion. This manuscript addresses the challenge of confirming that TMR has been inserted without corruption of functionality and with correct application of the expected TMR topology. The proposed verification method combines the usage of existing formal analysis tools with a novel search-detect-and-verify tool. Field programmable gate array (FPGA),Triple Modular Redundancy (TMR),Verification, Trust, Reliability,
Trust↗