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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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This is a presentation for students who will be participating in the App Development Challenge (ADC). This discussion tells the students the data format NASA will be using (which their software must be compatible with). This presentation contains only publicly available images and information, and is provided to help the students with their coding (that they will submit to NASA).
We are studying the development of space-flight compatible room-temperature electronics for the Lynx x-ray microcalorimeter (LXM) of the Lynx mission. The baseline readout technique for the LXM is microwave SQUID multiplexing. The key modules at room temperature are the RF electronics module and the digital electronics and event processor (DEEP). The RF module functions as frequency converters and mainly consists of local oscillators and I/Q mixers. The DEEP performs demultiplexing and event processing, and mainly consists of field-programmable gate arrays, ADCs, and DACs. We designed the RF electronics and DEEP to be flight ready, and estimated the power, size, and mass of those modules. There are two boxes each for the RF electronics and DEEP for segmentation, and the sizes of the boxes are 13 in: × 13 in: × 9 in: for the RF electronics and 15.5 in: × 11.5 in: × 9.5 in: for the DEEP. The estimated masses are 25.1 kg∕box for the RF electronics box and 24.1 kg∕box for the DEEP box. The maximum operating power for the RF electronics is 141 W or 70.5 W∕box, and for the DEEP box is 615 W or 308 W∕box. The overall power for those modules is 756 W. We describe the detail of the designs as well as the approaches to the estimation of resources, sizes, masses, and powers.
This paper reports recent single-event latchup results for a variety of microelectronic devices that include an ADC, OpAmp, EEPROM, CPLD, PWM, transceiver, voltage regulator, digital signal processor, step-down converter, buck controller and supervisory circuits. The data were collected to evaluate these devices for possible use in NASA ISS payloads.
The Laser Interferometer Space Antenna Pathfinder (LPF) main observable, labelled∆g, is the differential force per unit mass acting on the two test masses in free fall condition, after the contribution of all non-gravitational forces have been compensated. At low frequencies the differential force is compensated by an applied electrostatic actuation force,which then must be subtracted from the measured acceleration to obtain∆g. Any inaccuracy in the actuation force contaminates the residual acceleration. This study investigates the accuracy of the electrostatic actuation system and its impact on the LPF main observable. It is shown that the inaccuracy is mainly caused by the rounding errors in the waveform processing and also by the random error caused by the analog to digital converter (ADC) random noise in the control loop. Both errors are one order of magnitude smaller than the resolution of the commanded voltages. We developed a simulator based on the LPF design to compute the close-to-reality actuation voltages and consequently, the resulting actuation forces. The simulator is applied in post-processing the LPF data.
The Vorago Technologies RH-OBC-1 is a CubeSat Kit Bus compatible single board computer with a Vorago VA10820 ARM Cortex-M0 microcontroller at its core. The board also includes a set of common peripheral integrated circuits, like voltage regulators, non-volatile memories (NVM), an analog-to-digital converter (ADC), a watchdog/supervisor, and a Controller Area Network (CAN) bus transceiver. High-energy proton (200 MeV) testing was conducted at both board and component levels to investigate single-event effects.
This article investigates and identifies the baseline design and implementation of the digital baseband architecture for advanced deep space transponders. Trade studies on the selection of the number of bits for the analog-to-digital converter (ADC) and optimum sampling schemes are presented. In addition, the proposed optimum sampling scheme is analyzed in detail. Descriptions of possible implementations for the digital baseband (or digital front end) and digital phase-locked loop (DPLL) for carrier tracking are also described.
At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.
At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.
We are proposing a technology demonstration mission for JPL’s Inter-Satellite Optical Communicator (ISOC). The ISOC has the potential to enable up to 1 Gbps data rates over a distance up to 200 km in free space. Key features of the ISOC include full sky coverage and the ability to maintain multiple links simultaneously. The Q4 mission consists of (4) 6U CubeSats furnished with ISOCs to demonstrate high data rate communications among the spacecraft. More specifically, we seek to demonstrate the omnidirectionality of the ISOC by providing simultaneous optical links between one spacecraft and the other three. Q4 will be a demonstrator for small spacecraft swarm capabilities. Following a proposed deployment from the ISS, the CubeSats will utilize their onboard thrusters to enter their desired orbit. The orbit consists of one “leader” spacecraft in a circular orbit with a 400 km LEO altitude and three “follower” spacecraft in slightly elliptical orbits rotating azimuthally about the leader. The main mission will consist of three consecutive phases: First, the spacecraft will demonstrate pointing, acquisition, and tracking using newly developed protocols. Next, link establishment and different channel access methods (CDMA and TDMA) will be tested. Finally, Delay Tolerant Network protocols will be implemented to allow fast data sharing among the spacecraft. The distance between the communicating spacecraft will be increased as the mission progresses to characterize the link quality as a function of distance. All communications over the course of the mission will be recorded and analyzed on the ground using bit error rate as a metric for success. The current design for each the four Q4 CubeSats contains an XACT advanced ADCS system for precision beam pointing. Other components currently under consideration include MiPS cold gas thrusters for orbital maneuvering and gimbaled eHaWK 84W solar arrays. In this paper we present design considerations for the Q4 CubeSats, link budget calculations, results from preliminary mission analysis, and expected results.
The EXperiment for Cryogenic Large-Aperture Intensity Mapping (EXCLAIM) is a high-altitude balloon telescope designed to deepen our understanding of star formation in a cosmological context, shedding light on why the star formation rate declines and breaks away from the cosmological evolution of dark matter for redshifts z>2 [1]. EXCLAIM will operate at 420–540 GHz with a spectral resolution of R=512 to measure the integrated line emission from galaxies and the intergalactic medium (IGM), in particular CO and [CII] line emissions from the nearby universe out to redshifts of z~3.5. This approach is known as Intensity Mapping (IM), which provides efficient access to large cosmological volumes and redshifts with sensitivity limited by detector noise or photon background, while requiring modest apertures. The instrument will employ an array of six superconducting integrated grating-analog spectrometers (µ-Spec) with superconducting microwave kinetic inductance detectors (KIDs) in an all-cryogenic telescope (1.7 K) to achieve near background-limited sensitivity. Here, we present an overview of the EXCLAIM instrument and status, with emphasis on the Attitude Determination & Control System (ADCS) and the thermal system.
This paper reviews the flight experiences of the BioSentinel propulsion and Attitude Determination and Control System (ADCS) teams. BioSentinel is a 6U cubesat that launched as a secondary payload aboard the Space Launch System's (SLS) maiden flight in November of 2022 and is now operating in an Earth trailing heliocentric orbit. We discuss the mission's original GNC approach as well as several improvements made in-flight, in particular a novel approach to gyro bias estimation in the spacecraft’s sun safe controller. The development and flight experience of the spacecraft's RCS propulsion system is also discussed, along with modifications made to the momentum management approach in response to a failed thruster valve. Finally, we present lessons learned and recommendations for GNC design in future deep-space cubesats.
We present a field-programmable gate array (FPGA) implementation of a single photon-counting receive modem for a pulse position modulated signal. The modem is compliant with the Consultative Committee for Space Data Systems (CCSDS) High Photon Efficiency (HPE) Optical Communications Coding and Synchronization standard and is capable of a maximum data rate of 267 Mbps. The system is designed on a commercial off-the-shelf FPGA platform and utilizes superconducting nanowire single photon counting detectors, analog to digital converters (ADC s) to sample the detectors, and two FPGAs. Symbol timing recovery, photon counting, convolutional deinterleaving, and codeword synchronization areis performed in the first FPGA. The second FPGA performs iterative decoding on each codeword of the serially concatenated pulse position modulated (SCPPM) signal. A digital filter is included to compensate for timing jitter of the detector, and the decoder throughput can be modified adjusted through reconfigurable parallelization. The decoder also implements a resource-efficient, algorithmic polynomial interleaver and deinterleaver. Both FPGAs can be reconfigured to switch between pulse position modulation (PPM)-16 and PPM-32 with code rates 1/3, 1/2, and 2/3. In this paper, we describe the receiver architecture and FPGA implementation of the timing recovery loop and SCPPM decoder, FPGA utilization for the different modes, and receive modem characterization test results.
This paper reviews the flight experiences of the BioSentinel propulsion and At-titude Determination and Control System (ADCS) teams. BioSentinel, a 6U CubeSat, launched as a secondary aboard the Space Launch System (SLS) maid-en flight in November of 2022 and is now operating in an Earth trailing helio-centric orbit. The development and performance of a novel approach to gyro bias estimation in the spacecraft’s Sun safe controller is discussed in detail. Further-more, the development and in-flight experience with the spacecraft’s propulsion system is discussed. Finally, we present the development and execution of an angular momentum management approach developed in flight after a propulsion system valve failure.
This presentation reviews the flight experiences of the BioSentinel propulsion and At-titude Determination and Control System (ADCS) teams. BioSentinel, a 6U CubeSat, launched as a secondary aboard the Space Launch System (SLS) maid-en flight in November of 2022 and is now operating in an Earth trailing helio-centric orbit. The development and performance of a novel approach to gyro bias estimation in the spacecraft’s Sun safe controller is discussed in detail. Further-more, the development and in-flight experience with the spacecraft’s propulsion system is discussed. Finally, we present the development and execution of an angular momentum management approach developed in flight after a propulsion system valve failure.
We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.
One of the major scientific goals of the Deep Underground Neutrino Experiment (DUNE) is to detect and measure the neutrino flux from galactic core-collapse supernovae. These neutrinos, which exist in the low energy range of up to a few tens of MeV and are responsible for carrying away over 99% of the gravitational binding energy of the supernova, provide an opportunity to study the end of life evolution of massive stars, as well as unique properties and interactions of neutrinos. Because galactic supernovae are expected to occur only on the timespan of every few decades, it is crucial that DUNE is able to detect supernova neutrino interactions when they occur. However, detecting these supernova interactions requires sifting through a large amount of data, and DUNE detectors require a trigger to signal when supernova neutrino events occur. Machine learning provides a potential approach to creating this trigger. This project generates ADC and ground truth images of neutrino interactions in a LArTPC detector as simulated by the Model of Argon Reaction Low Energy Yields (MARLEY) to be used for machine learning. The eventual goal of this work is to facilitate DUNE s detection of supernova neutrino interactions by building a machine learning pipeline to train the trigger algorithm.
One of the major scientific goals of the Deep Underground Neutrino Experiment (DUNE) is to detect and measure the neutrino flux originating from galactic core-collapse supernovae. These neutrinos provide an opportunity to study the end of life evolution of massive stars, and reveal information about the structure of core-collapse that is not visible in observations of the electromagnetic spectrum. Because of the rarity of these events, it is crucial that DUNE is able to detect supernova neutrino interactions when they occur. However, this will require sifting through a large quantity of data, motivating the development of a trigger algorithm to identify significant events and discard irrelevant data. Machine learning provides a potential approach to building this trigger. This project generates ADC and ground truth images of simulated neutrino interactions in a LArTPC detector to be used for machine learning, and uses them to train a sparse Convolutional Neural Network (C NN). The performance of this model when applied to the task of pixel classification based on interaction type is examined. This project found that the sparse CNN approach has the potential to have high accuracy in pixel classification, meaning it may be highly relevant to the development of a supernova neutrino trigger for the DUNE far detector.
A programmable signal processor-based credited safety control that calculates pulsed beam power based on beam kinetic energy and charge was designed as part of the Proton Power Upgrade (PPU) project at the Spallation Neutron Source (SNS). The system must reliably shut off the beam if the average power exceeds 2.145 MW averaging over 60 seconds. System calibration requires pedigree in measurements, calibration setup, and calculations. This paper discusses the calibration of the analog beam signal components up to and including the Analog Digital Convertors (ADCs) for implementation into the Safety Programmable Logic Controllers (PLCs) and Field Programmable Gate Arrays (FPGAs).