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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Upcycling Polyethylene Waste into Hybrid Graphitic Porous Carbon Materials Used in High‐Performance Zinc‐Ion Hybrid Capacitors

Polyethylene (PE) waste is a challenge to upcycle into useful materials because this plastic tends to decompose into volatile compounds when heated at relatively low temperatures. In this work, mixtures of PE wastes into a hybrid graphitic porous carbon (HGPC) by a thermal oxidation pretreatment step, with assistance of an inert solid additive (KCl), to functionalize, crosslink, and stabilize the PE waste followed by carbonization and catalytic graphitization steps with a potassium carbonate catalyst, are upcycled. The PE waste‐derived HGPC (PW‐HGPC) has a hybrid structure composed of graphene‐like carbon nanosheets grown on the surface of carbon particles, high porosity with specific surface area, up to 1,763 m 2 g −1 , and good graphitic degree with average Raman I 2D / I G ratios of 0.53. When used as cathode material for zinc‐ion hybrid capacitors, this PW‐HGPC exhibits an excellent specific capacity, up to 126.7 mAh g −1 , at high mass loading of 10 mg cm −2 . Moreover, PW‐HGPC exhibits remarkable cycling stability with capacity retention of >94% after 10 000 cycles. Additionally, the KCl is recycled and reused over five times. This method provides a new solution for upcycling PE wastes into high value‐added carbon materials, not only for zinc‐ion hybrid capacitors but also for other electrochemical energy storage device applications.

hybrid graphitic porous carbon↗
DOE OSTI2020

Evaluation of the DC bus link capacitors and power transistor modules in the qualification testing of PV inverters

To achieve useful, fair, and cost-effective design qualification and type approval testing for PV inverters, two procedures were developed and demonstrated to evaluate the bus link capacitors and power transistor—and where applicable, its module—for long-term reliability. We evaluate the inverter under simulated use conditions with heat run tests to find the highest operating temperatures reached by these components. The procedures are demonstrated in this study with a 4-kVA class string inverter. The maximum temperature of the DC bus link capacitors was determined to be 76.4°C when the ambient temperature was at the inverter's maximum rated temperature of 60°C with derating occurring. On the other hand, the power transistor module's maximum temperature using the heat sink temperature as the index, 92.6°C, occurred in an ambient of 40.8°C when derating was not occurring. The conditions found for upper temperatures exhibited by these components are, respectively, proposed for implementation in the dry heat and thermal cycling tests in the IEC 62093 “Power conversion equipment for photovoltaic systems – Design qualification testing” international standard draft so that the levels applied in the tests are in proportion to those experienced in the field. Finally as a result, fairer evaluation of inverter reliability is realized.

14 SOLAR ENERGY↗
DOE OSTI2023

A Reconfigurable Planar Capacitor Sensor for Thru the Jacket Dielectric Constant Measurement of Cable Insulation

Planar capacitor sensors have been proposed to measure the aging-related dielectric constant variation of the jacket or insulation materials of cables. Although capacitor sensors have been used to monitor the aging of cable insulation by removing the jacket, through the jacket measurement of cable insulation dielectric constant variation is difficult because once the sensor is placed on the jacket it would either measure the aging of the jacket or that of the jacket and insulation together. A reconfigurable sensor along with innovative cable-specific models could be used to determine the jacket and insulation aging using the same sensor. For the proposed novel reconfigurable sensor, the electric field penetration depth is changed by activating and deactivating PIN diode switches. In one instance, the sensor measures the dielectric constant variation of the jacket, while in the next, it measures the dielectric constant variation of both the jacket and the insulation. Here, by leveraging previously developed capacitance estimation models from large-scale finite element simulations for a specific cable, these two sets of measurement data are used to evaluate the aging-related dielectric constant variation of the insulation. Experimental data from aged cable specimens are presented to demonstrate the operation of the sensor.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Upcycling Polyethylene Waste Into Hybrid Graphitic Porous Carbon Materials Used in High-Performance Zinc-Ion Hybrid Capacitors

Polyethylene (PE) waste is a challenge to upcycle into useful materials because this plastic tends to decompose into volatile compounds when heated at relatively low temperatures. In this work, we report a chemical process that addresses this challenge by converting mixtures of linear low-density polyethylene (LLDPE), low-density polyethylene (LDPE), and high-density polyethylene (HDPE) waste into a hybrid graphitic porous carbon (HGPC) that can be used as a zinc-ion hybrid capacitor cathode. The process uses a low temperature thermal oxidation pre-treatment step, with assistance of an inert solid additive (KCl) to increase the effective surface area of the PE melt, to functionalize, cross-link, and stabilize the PE waste followed by carbonization and catalytic graphitization steps at higher temperatures with a potassium carbonate (K2CO3) catalyst. The PE waste derived HPGC (PW-HPGC) has a hybrid structure composed of graphene-like carbon nanosheets grown on the surface of carbon particles, high porosity with the Brunauer–Emmett–Teller (BET) specific surface area up to 1,763 m2g-1, and good graphitic degree with average Raman I2D/IG ratios of 0.53. When used as a cathode material for zinc-ion hybrid capacitors, this PW-HGPC exhibits an excellent specific capacity up to 126.7 mAhg-1 at high mass loading of 10 mgcm-2. Moreover, PW-HGPC exhibits remarkable cycling stability with capacity retention of >94% after 10,000 cycles at a current density of 2.0 A g-1.

hybrid graphitic porous carbon↗
NASA NTRS2014

Insulation Resistance and Leakage Currents in Low-Voltage Ceramic Capacitors with Cracks

Measurement of insulation resistance (IR) in multilayer ceramic capacitors (MLCCs) is considered a screening technique that ensures the dielectric is defect-free. This work analyzes the effectiveness of this technique for revealing cracks in ceramic capacitors. It is shown that absorption currents prevail over the intrinsic leakage currents during standard IR measurements at room temperature. Absorption currents, and consequently IR, have a weak temperature dependence, increase linearly with voltage (before saturation), and are not sensitive to the presence of mechanical defects. In contrary, intrinsic leakage currents increase super-linearly with voltage and exponentially with temperature (activation energy is in the range from 0.6 eV to 1.1 eV). Leakage currents associated with the presence of cracks have a weaker dependence on temperature and voltage compared to the intrinsic leakage currents. For this reason, intrinsic leakage currents prevail at high temperatures and voltages, thus masking the presence of defects.

dielectric polarization↗
NASA NTRS2016

Degradation of Leakage Currents and Reliability Prediction for Tantalum Capacitors

Two types of failures in solid tantalum capacitors, catastrophic and parametric, and their mechanisms are described. Analysis of voltage and temperature reliability acceleration factors reported in literature shows a wide spread of results and requires more investigation. In this work, leakage currents in two types of chip tantalum capacitors were monitored during highly accelerated life testing (HALT) at different temperatures and voltages. Distributions of degradation rates were approximated using a general log-linear Weibull model and yielded voltage acceleration constants B = 9.8 +/- 0.5 and 5.5. The activation energies were Ea = 1.65 eV and 1.42 eV. The model allows for conservative estimations of times to failure and was validated by long-term life test data. Parametric degradation and failures are reversible and can be annealed at high temperatures. The process is attributed to migration of charged oxygen vacancies that reduce the barrier height at the MnO2/Ta2O5 interface and increase injection of electrons from the MnO2 cathode. Analysis showed that the activation energy of the vacancies' migration is ~ 1.1 eV.

acceleration factors↗
NASA NTRS2016

Insulation Resistance and Leakage Currents in Low-Voltage Ceramic Capacitors with Cracks

Measurement of insulation resistance (IR) in multilayer ceramic capacitors (MLCCs) is considered a screening technique that ensures the dielectric is defect-free. This work analyzes the effectiveness of this technique for revealing cracks in ceramic capacitors. It is shown that absorption currents prevail over the intrinsic leakage currents during standard IR measurements at room temperature. Absorption currents, and consequently IR, have a weak temperature dependence, increase linearly with voltage (before saturation), and are not sensitive to the presence of mechanical defects. In contrary, intrinsic leakage currents increase super-linearly with voltage and exponentially with temperature (activation energy is in the range from 0.6 eV to 1.1 eV). Leakage currents associated with the presence of cracks have a weaker dependence on temperature and voltage compared to the intrinsic leakage currents. For this reason, intrinsic leakage currents prevail at high temperatures and voltages, thus masking the presence of defects.

testing↗
NASA NTRS2017

Ceramic Capacitor Delamination Problem

Update on ceramic capacitors issues since last years meeting. To including the story behind the issues behind the TIRS and SDO leaky capacitors.

Ceramic Capacitor↗
NASA NTRSDate not supplied

Infant Mortality and Wear-Out Failures in Polymer and MnO2 Tantalum Capacitors

Reliability testing of modern tantalum capacitors shows the presence of both types, infant mortality (IM) and wearout (WO) failures. To assure reliable operation, the probability of IM failures should be reduced to below the specified level, and the time of WO inception should be greater than the required useful life of the parts at operation conditions. In this work, several types of MnO2 and polymer cathode tantalum capacitors have been tested at highly accelerated conditions to assess voltage acceleration factors, determine adequate burn-in conditions, and assess the useful life. A modified time dependent dielectric breakdown (TDDB) model has been suggested to explain both types of failure, and a physical mechanism of degradation that is based on migration and reactions of oxygen vacancies explains increase of the defect related, IM failures with the level of stress.

tantalum capacitors↗
NASA NTRS2023

Metrics for Anomalous Charging currents in Polymer Tantalum Capacitors

Anomalous charging currents (ACC) in polymer tantalum capacitors may appear as a temporary short circuit that can last for dozens of milliseconds, cause failures to the parts, or cause malfunctions to fast operating electronic systems. Currently, there is no standard technique or set of metrics to evaluate the level of ACC which compares results obtained by different users and manufacturers. In this work, ACC in different types of capacitors were characterized by analysis of current transients during the constant voltage ramp or power surge testing (PST) techniques. It is shown that although the shape of transients may vary at different test conditions, the transfer charge and energy remain practically the same. The level of ACC is characterized by the energy dissipated in the part during PST. Variations of the dissipated energy with moisture content, test temperature, and voltage are evaluated. Effects of different reflow soldering conditions and long-term (up to 3000 hours) storage at 125 °C are discussed.

polymer tantalum capacitor↗
DOE OSTI2020

DC Link Capacitor Reduction with Feedforward Control in Series-Series Compensated Wireless Power Transfer Systems

This paper presents the use of feedforward control to reduce the input side DC link capacitance of series-series compensated wireless power transfer (WPT) systems. Compared to conventional control schemes for WPT systems, the proposed feedforward-based approach achieves significant reduction in the DC link capacitor without any complicated voltage or current sensing requirements from the secondary side. This results in more compact hardware architecture. The proposed method shows minimal increase in the turn-on switching loss of the inverter. The switching loss is analyzed, and detailed results are presented relating the switching loss to the DC link capacitance and voltage ripple for proper tradeoff between losses and capacitor size. Simulation and experimental results presented validate the proposed scheme.

Mukherjee, Subho↗
DOE OSTI2021

Efficiency Optimization of Dual Active Bridge Converter Based on dV/dt Snubber Capacitors

This paper presents a lossless regenerative dV/dt snubber circuit for PWM converters to achieve high-efficiency high power-density without significant cost and reliability penalties. The dV/dt snubber employs lossless capacitors for each MOSFET device in a converter to provide an additional path to store the switching energy during turn-off transient and decrease the actual turn-off loss of the MOSFET channel. A novel mathematical turn-off loss model is built to separate the actual turn-off loss of the MOSFET channel and the recycling switching energy stored in the total equivalent output capacitance including Coss, the dV/dt snubber, and etc. Necessary snubber optimization strategy is proposed in order to balance the turn-off loss with ZVS operation range and deadtime conduction loss, and thereby achieving an optimal efficiency performance. To prove the validity and accuracy of the novel turn-off loss model and optimization strategy, the dV/dt snubber has been incorporated into a 1.3kV/200kW DC/DC and a 1kV/70kVA DC/AC PWM converters. Experimental results are given to demonstrate the validity of the proposed dV/dt snubber capacitors and optimization strategy.

Xu, Wei↗
DOE OSTI2024

Predictive Control to Further Reduce DC-Link Capacitor Current Stress for Segmented Inverter

Two three-phase interleaved inverters have been used in traction drive applications to reduce the current stress in a DC link capacitor bank. In such applications, either carrier-based or space vector modulation is used to select the optimum switching sequences, and the results show 50% less capacitor current than that of a single three-phase inverter. The switching state selection process for this inverter is tedious, and there has been no research to find the optimal switching state. To overcome this challenge, this research employed a simple finite set model predictive control to select the optimum switching sequence for a dual three-phase interleaved topology, called a segmented inverter. The results show that the predictive control algorithm can provide a simple solution and can reduce the current stress by 27% compared with traditional modulation techniques for the segmented inverters.

Ribeiro, Pedro↗
DOE OSTI2024

Increasing Multilayer Ceramic Capacitor Lifetime With Bipolar Voltage Cycling

Enhancing the lifetime of multilayer ceramic capacitors (MLCCs) is critical in many aerospace, naval, or electrical grid applications, where device failure could lead to catastrophic consequences. The migration of oxygen vacancies from the ceramic to the electrode interface under constant bias is known to reduce the lifetime of oxide-based MLCCs. Bias cycling presents an opportunity to enhance MLCC lifetime by reducing oxygen vacancy migration. The ideal frequency range is expected to lie between frequencies low enough to avoid self-heating but high enough to avoid interfacial defect formation. However, the impact of low-frequency bipolar voltage cycling (BVC) on MLCC degradation mechanisms has not been well studied. This work investigates the impact of periodic BVC on the degradation of MLCCs through highly accelerated lifetime testing (HALT) on X7R capacitors. HALT tests were conducted at 255 °C and 60 V using different switching frequencies: 0 (dc), 0.1, 2.5, and 10 Hz. BVC was found to improve the lifetime of MLCCs compared to dc test conditions. MLCCs tested at 10-Hz BVC showed a 311% increase in average time to failure compared to the dc case. Impedance spectroscopy shows that BVC decreases the rate of resistance degradation within MLCCs, indicating that oxygen vacancy migration to the electrodes is mitigated. The impedance spectra taken on BVC samples highlight how grain boundaries play a vital role in trapping oxygen vacancies. Periodic cycling causes oxygen vacancies to become trapped at grain boundaries, resulting in oxygen vacancies taking longer to reach the electrode interface and thus increasing MLCC lifetime. This work highlights not only how BVC can be used to increase MLCC lifetime but also how periodically cycling MLCCs could increase lifetime in extreme environments, such as at elevated temperatures and electric fields.

Chuong, Kayla Y.↗
DOE OSTI2025

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗