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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Electron-phonon coupling induced intrinsic Floquet electronic structure

Floquet states are a topic of intense contemporary interest, which is often induced by coherent external oscillating perturbation (e.g., laser, or microwave) which breaks the continuous time translational symmetry of the systems. Usually, electron–phonon coupling modifies the electronic structure of a crystal as a non-coherent perturbation and seems difficult to form Floquet states. Surprisingly, we found that the thermal equilibrium electron–phonon coupling in M(MoS) 3 and M(MoSe) 3 (where M is a metallic element) exhibits a coherent behavior, and the electronic structure can be described by the Floquet theorem. Such a coherent Floquet state is caused by a selective giant electron–phonon coupling, with thermodynamic phonon oscillation serving as a driving force on the electronic part of the system. The quasi-1D Dirac cone at the Fermi energy has its band gap open and close regularly. Similarly, the electric current will oscillate even under a constant voltage.

36 MATERIALS SCIENCE↗
NASA NTRS2020

Body of Knowledge for Gallium Nitride Power Electronics

Gallium nitride (GaN), a wide bandgap (WBG) semiconductor, has emerged as a very promising material for electronic components due to the tremendous advantages it offers compared to silicon (Si), such as power capability, extreme temperature tolerance, and high frequency operation. This report serves as a body of knowledge (BOK) in reference to the development and current status of GaN technology obtained via literature and industry surveys. It provides a listing of the major manufacturers and their capabilities, as well as government, industry, and academic parties interested in the technology. The document also discusses GaN’s applications in the area of power electronics, in particular those geared for space missions. Finally, issues relevant to the reliability of GaN-based electronic parts are addressed and limitations affecting the full utilization of this technology are identified. This BOK focuses mainly on power applications for GaN, but will also briefly mention radio frequency (RF) applications for completeness.

Gallium Nitride Power Electronics↗
NASA NTRS2014

Aeroflex Technology as Class-Y Demonstrator

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Suh, Jong-ook↗
NASA NTRS2000

A Boundary Scan Test Vehicle for Direct Chip Attach Testing

To facilitate the new faster, better and cheaper spacecraft designs, smaller more mass efficient avionics and instruments are using higher density electronic packaging technologies such as direct chip attach (DCA). For space flight applications, these technologies need to have demonstrated reliability and reasonably well defined fabrication and assembly processes before they will be accepted as baseline designs in new missions. As electronics shrink in size, not only can repair be more difficult, but 49 probing" circuitry can be very risky and it becomes increasingly more difficult to identify the specific source of a problem. To test and monitor these new technologies, the Direct Chip Attach Task, under NASA's Electronic Parts and Packaging Program (NEPP), chose the test methodology of boundary scan testing. The boundary scan methodology was developed for interconnect integrity and functional testing at hard to access electrical nodes. With boundary scan testing, active devices are used and failures can be identified to the specific device and lead. This technology permits the incorporation of "built in test" into almost any circuit and thus gives detailed test access to the highly integrated electronic assemblies. This presentation will describe boundary scan, discuss the development of the boundary scan test vehicle for DCA and current plans for testing of direct chip attach configurations.

Parsons, Heather A.↗
NASA NTRS2014

MSFC/EV44 Natural Environment Capabilities

The Natural Environments Branch at Marshall Space Flight Center is an integral part of many NASA satellite and launch vehicle programs, providing analyses of the space and terrestrial environments that are used for program development efforts, operational support, and anomaly investigations. The space environment capabilities of the Natural Environments Branch at MSFC will be presented. These capabilities include model development, analysis of space and terrestrial related data, spacecraft charging anomaly investigations, surface charging modeling (e.g., Nascap-2k), space environment definition and radiation assessments for electronic parts. All aspects of space and terrestrial design are implemented with the goal of devising missions that are successful from launch to operations in the space environment of LEO, polar, GEO, and interplanetary orbits. We will show examples of recent applications of branch capabilities to NASA missions.

Parker, L. Neergaard↗
NASA NTRS2010

FPGA NEPP : FY09 summary report

This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for re-programmable field programmable gate arrays (FPGAs). The FY09 task was divided into three efforts: 1. Device physics-based design modifications 2. Contention study of Xilinx Virtex-4 3. IDDQ study of Actel A54SX The FY09 NEPP FPGA study was organized into these three sections in recognition of the continued and increasing importance of FPGAs to NASA. FPGAs represent the state of the art in electronic components with millions and millions of transistors integrated into a single device. Modern NASA spacecraft design has dozens and dozens of FPGAs implemented onboard. FPGAs are used in critical command and data handling, instrument control and monitoring, and communications protocols, to name just a few. The reliability of FPGAs is fundamental to mission success for NASA.

Sheldon, Douglas↗
DOE OSTI2023

Elimination of the bias-stress effect in ligand-free quantum dot field-effect transistors

Field-effect transistors (FETs) made from colloidal quantum dot (QD) solids commonly suffer from current–voltage hysteresis caused by the bias-stress effect (BSE), which complicates fundamental studies of charge transport in QD solids and the use of QD FETs in electronics. Here, we show that the BSE can be eliminated in n-channel PbSe QD FETs by first removing the QD ligands with a dose of H 2 S gas and then infilling the QD films with alumina by atomic layer deposition (ALD). The H 2 S-treated, alumina-infilled FETs have stable, hysteresis-free device characteristics (total short-term stability), indefinite air stability (total long-term stability), and a high electron mobility of up to 14 cm 2 V −1 s −1 , making them attractive for QD circuitry and optoelectronic devices. The BSE-free devices are utilized to conclusively establish the dependence of the electron mobility on temperature and QD diameter. We demonstrate that the BSE in these devices is caused by both electron trapping at the QD surface and proton drift within the film. The H 2 S/alumina chemistry produces ligand-free PbSe/PbS/Al 2 O 3 interfaces that lack the traps that cause the electronic part of the BSE, while full alumina infilling stops the proton motion responsible for the ionic part of the BSE. In conclusion, our matrix engineering approach should aid efforts to eliminate the BSE, boost carrier mobilities, and improve charge transport in other types of nanocrystal solids.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS2011

Pulsed Laser System to Simulate Effects of Cosmic Rays in Semiconductor Devices

Spaceflight system electronic devices must survive a wide range of radiation environments with various particle types including energetic protons, electrons, gamma rays, x-rays, and heavy ions. High-energy charged particles such as heavy ions can pass straight through a semiconductor material and interact with a charge-sensitive region, generating a significant amount of charge (electron-hole pairs) along their tracks. These excess charges can damage the device, and the response can range from temporary perturbations to permanent changes in the state or performance. These phenomena are called single event effects (SEE). Before application in flight systems, electronic parts need to be qualified and tested for performance and radiation sensitivity. Typically, their susceptibility to SEE is tested by exposure to an ion beam from a particle accelerator. At such facilities, the device under test (DUT) is irradiated with large beams so there is no fine resolution to investigate particular regions of sensitivity on the parts. While it is the most reliable approach for radiation qualification, these evaluations are time consuming and costly. There is always a need for new cost-efficient strategies to complement accelerator testing: pulsed lasers provide such a solution. Pulsed laser light can be utilized to simulate heavy ion effects with the advantage of being able to localize the sensitive region of an integrated circuit. Generally, a focused laser beam of approximately picosecond pulse duration is used to generate carrier density in the semiconductor device. During irradiation, the laser pulse is absorbed by the electronic medium with a wavelength selected accordingly by the user, and the laser energy can ionize and simulate SEE as would occur in space. With a tightly focused near infrared (NIR) laser beam, the beam waist of about a micrometer can be achieved, and additional scanning techniques are able to yield submicron resolution. This feature allows mapping of all of the sensitive regions of the studied device with fine resolution, unlike heavy ion experiments. The problematic regions can be precisely identified, and it provides a considerable amount of information about the circuit. In addition, the system allows flexibility for testing the device in different configurations in situ.

Aveline, David C.↗
NASA NTRS2021

Systems Engineering and Assurance Modeling (SEAM): A Web-Based Solution for Integrated Mission Assurance

We present an overview of the Systems Engineering and Assurance Modeling (SEAM) platform, a web-browser-based tool which is designed to help engineers evaluate the radiation vulnerabilities and develop an assurance approach for electronic parts in space systems. The SEAM framework consists of three interconnected modeling tools, a SysML compatible system description tool, a Goal Structuring Notation (GSN) visual argument tool, and Bayesian Net and Fault Tree extraction and export tools. The SysML and GSN sections also have a coverage check application that ensures that every radiation fault identified on the SysML side is also addressed in the assurance case in GSN. The SEAM platform works on space systems of any degree of radiation hardness but is especially helpful for assessing radiation performance in systems with commercial-off-the-shelf (COTS) electronic components.

SEAM↗
NASA NTRS2009

Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing it to a total of 12 cycles between -195 C and +250 C. Following the cycling activity, measurements were performed again at the test temperatures of -195 C, +21 C, and +250 C.

Patterson, Richard↗
NASA NTRS2023

Extended Temperature Operation of Isolated, Precision Gate Driver, ADuM4120

Electronics used in space missions encounter exposure to extreme temperatures and operation under wide thermal swings. Most commercial-off-the-shelf (COTS) devices are not designed to function under such extreme conditions and very little data exist on their performance outside their specified range of operation. Extending the temperature range at which electronic parts can operate reliably leads to potential benefits resulting in improving reliability, reducing mass/weight, and simplifying thermal design due to elimination of thermal control elements and fewer parts count. In this work, the performance of an isolated, precision gate driver for controlling power-level transistors, including gallium nitride (GaN) and silicon carbide (SiC) devices, was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance for potential use of this device in space exploration missions under extreme temperature conditions.

Wide Bandgap Power Electronics↗
NASA NTRS2015

Single-Event Effects in Silicon Carbide Power Devices

This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

heavy-ion single-event effects↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
DOE OSTI2020

TurboRVB: A many-body toolkit for ab initio electronic simulations by quantum Monte Carlo

TurboRVB is a computational package for ab initio Quantum Monte Carlo (QMC) simulations of both molecular and bulk electronic systems. The code implements two types of well established QMC algorithms: Variational Monte Carlo (VMC) and diffusion Monte Carlo in its robust and efficient lattice regularized variant. A key feature of the code is the possibility of using strongly correlated many-body wave functions (WFs), capable of describing several materials with very high accuracy, even when standard mean-field approaches [e.g., density functional theory (DFT)] fail. The electronic WF is obtained by applying a Jastrow factor, which takes into account dynamical correlations, to the most general mean-field ground state, written either as an antisymmetrized geminal power with spin-singlet pairing or as a Pfaffian, including both singlet and triplet correlations. This WF can be viewed as an efficient implementation of the so-called resonating valence bond (RVB) Ansatz, first proposed by Pauling and Anderson in quantum chemistry [L. Pauling, The Nature of the Chemical Bond (Cornell University Press, 1960)] and condensed matter physics [P.W. Anderson, Mat. Res. Bull 8, 153 (1973)], respectively. The RVB Ansatz implemented in TurboRVB has a large variational freedom, including the Jastrow correlated Slater determinant as its simplest, but nontrivial case. Moreover, it has the remarkable advantage of remaining with an affordable computational cost, proportional to the one spent for the evaluation of a single Slater determinant. Therefore, its application to large systems is computationally feasible. The WF is expanded in a localized basis set. Several basis set functions are implemented, such as Gaussian, Slater, and mixed types, with no restriction on the choice of their contraction. The code implements the adjoint algorithmic differentiation that enables a very efficient evaluation of energy derivatives, comprising the ionic forces. Thus, one can perform structural optimizations and molecular dynamics in the canonical NVT ensemble at the VMC level. For the electronic part, a full WF optimization (Jastrow and antisymmetric parts together) is made possible, thanks to state-of-the-art stochastic algorithms for energy minimization. In the optimization procedure, the first guess can be obtained at the mean-field level by a built-in DFT driver. The code was efficiently parallelized by using a hybrid MPI-OpenMP protocol, which is also an ideal environment for exploiting the computational power of modern Graphics Processing Unit accelerators.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS2000

Assessment and Assurance of Microelectronics Packaging Technology of Microelectromechanical Systems (MEMS)

Microelectromechanical systems (MEMS) have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, etc. Standard semiconductor microelectronics packaging needs the integrated circuits to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the packaging technology. In the case of MEMS the microstructures (active elements) often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it 'measures to assure the MEMS technology by lowering the risk to zero. MEMS technology has a major application in developing a microspacecraft for space systems provided assurance of MEMS technology is sufficiently addressed nondestructively. This technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's safety and mission assurance goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively by teaming-up with the other NASA centers using the limited resources available. This paper discusses the latest developments in the MEMS technology and challenging issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices based on silicon, poly-silicon, and other materials for microspacecraft applications considering the space environment and reliability assurance qualification guidelines in perspective. Acknowledgments: The above research work is supported by the NASA Electronics Parts and Packaging Program (NEPP) and performed by the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA under a contract with the NASA - Code Q for the Office of Safety and Mission Assurance Program 323-79.

Ramesham, Rajeshuni↗
DOE OSTI2022

Experiments and modelling of adhesive failure initiation of an epoxy underfill: a study of electronic packaging survivability

Epoxy underfills can be implemented in electronic packaging to enhance solder joint reliability of surface mounted components. However, it is important for an engineer to have a failure criterion that can be used for failure predictions and redesign of electronic assemblies. For this study, data from epoxy bond failure in mock electronic part assemblies were correlated to finite element analyses to predict adhesive failure initiation. Experiments were performed to determine failure loads for various loading locations and nonlinear viscoelastic analyses were performed for the same loading locations to determine a maximum principal strain failure parameter. Predictions showed that a maximum principal strain failure parameter defined from one test could be used as an indicator of adhesive failure of an epoxy bond undergoing other modes of loading. Failure initiation predictions matched experimental data using a maximum principal strain failure parameter for an epoxy bond undergoing mixed modes of loading for both unfilled and alumina oxide filled 828DEA epoxy. Such experimental setup is deemed appropriate for future epoxy testing.

42 ENGINEERING↗