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A monolithic gain control amplifier for Ka-band has been developed based on 0.25 micron-gate-length dual-gate FETs fabricated on ion-implanted material. A single-stage monolithic amplifier gives a gain of 6 dB at 31 GHz including fixture losses with a gain control range of over 20 dB. The device and IC design and fabrication are described.
New circuit requires no heat sink and is compact. Parts cost no more than those of linear regulator. Switching regulator repeatedly causes solenoid current to build up to maximum level, then to decay to minimum level: thus current ripples about commanded intermediate level. FET's dissipate significant amounts of power only during brief turn-on and turn-off intervals.
An 8.5 GHz dual-channel, dual-polarization traveling-wave maser (TWM) amplifier was installed in the XKR solar system radar cone at DSS 14. The TWM is based on the Blk IIA 8.45 GHz maser structure, with two of the four maser stages being used for each channel, and each maser half then followed by a high-performance GaAs FET amplifier to achieve the desired net gain. A shortened low-noise input waveguide and an orthogonal-mode junction which is cooled to 4.5 K feeds each amplifier chain. The rotation of an external polarizer permits the polarization of each channel to be defined as either linear or circular. A circular waveguide switch was also developed to provide for noise calibration and to protect the maser from incident transmitter power.
An improved HgCdTe photomixer technology was demonstrated employing a p-i-n photodiode structure. The i-region was near intrinsic n-type HgCdTe; the n-region was formed by B+ ion implantation; and the p-region was formed either by a shallow Au diffusion or by a Pt Schottky barrier. Experimental devices in a back-side illuminated mesa diode configuration were fabricated, tested, and delivered. The best photomixer was packaged in a 24-hour LN2 dewar along with a cooled GaAs FET preamplifier. Testing was performed by mixing black-body radiation with a CO2 laser beam and measuring the IF signal, noise, and signal-to-noise ratio in the GHz frequency range. Signal bandwidth for this photomixer was 1.3 GHz. The heterodyne NEP was 4.4 x 10 to the -20 W/Hz out to 1 GHz increasing to 8.6 x 10 to the -10 W/Hz at 2 GHz. Other photomixers delivered on this program had heterodyne NEPs at 1 GHz ranging from 8 x 10 to the -20 to 4.4 x 10 to the -19 W/Hz and NEP bandwidths from 2 to 4 GHz.
This article shows the design aspects of a 2.385 GHz low noise preamplifier with a .7 dB noise figure and 16.5 dB gain using the NE 67383 FET. The design uses a unique method in matching the input which achieves optimum noise figure and unconditional stability.
Modulation-doped InAlAs/InGaAs/InP structures were grown by molecular beam epitaxy and fabricated into FETs with excellent RF gain performance. The intrinsic transconductance was about 400 mS/mm at 300 K. Current gain cutoff frequencies of up to 26.5 GHz were obtained in 1-micron gate devices. Extremely small S12 and large S21 led to a very large F(max) of 62 GHz. These results represent the best reported figures for 1-micron devices in this material system, and slightly better than those obtained in recently developed pseudomorphic modulation-doped field effect transistors.
The Very Large Array (VLA) is being equipped to receive telemetry from Voyager 2 during the Neptune encounter in 1989. Cryogenically cooled amplifiers are being installed on each of the 27 antennas. These amplifiers are currently a mix of field effect transistors (FETs) and high electron mobility transistors (HEMTs) and exhibit zenith system temperatures that range from 30 to 52 K. The system temperatures and aperture efficiencies determined during the past year are summarized. The nominal values of the noise diode calibration are compared with derived values made under the assumption of a uniform atmosphere over the array. Gain values are determined from observations of unresolved radio sources whose flux densities are well known. The tests suggest that the completed VLA will have a ratio of gain to system temperature that is approximately 4.4 dB above that of a single 64 m antenna of the Deep Space Network.
Two modules of gallium-doped germanium (Ge:Ga) infrared detectors with integrated multiplexing readouts and supporting drive electronics were designed and tested. This development investigated the feasibility of producing two-dimensional Ge:Ga arrays by stacking linear modules in a housing capable of providing uniaxial stress for enhanced long-wavelength response. Each module includes 8 detectors (1x1x2 mm) mounted to a sapphire board. The element spacing is 12 microns. The back faces of the detector elements are beveled with an 18 deg angle, which was proved to significantly enhance optical absorption. Each module includes a different silicon metal-oxide semiconductor field effect transistor (MOSFET) readout. The first circuit was built from discrete MOSFET components; the second incorporated devices taken from low-temperature integrated circuit multiplexers. The latter circuit exhibited much lower stray capacitance and improved stability. Using these switched-FET circuits, it was demonstrated that burst readout, with multiplexer active only during the readout period, could successfully be implemented at approximately 3.5 K.
By combining high-quality mesa photovoltaic indium antimonide detector material with a silicon x-y FET switch multiplexer, a useful infrared area detector has been developed. This device is intended for low-background applications, where high sensitivity is required. Initial characterization of the detector at 80 K showed a KTC limited read noise of less than 1000 electrons, good dark current, responsivity uniformity, and a maximum readout rate of 10 MHz. The hybrid mating technology has sufficient precision to allow expansion to a 256 x 256 format. The dark current in the detector material is sufficiently low to allow full-frame integration, even with arrays as large as 256 x 256 elements.
NASA's Kuiper Airborne Observatory, which is a C-141 transport aircraft equipped with a 90-cm, all-reflective altazimuth telescope, has been engaged in the Kuiper Infrared Technology Experiment. Attention is presently given to the Experiment's flight series for state-of-the-art two-dimensional, 500-element arrays that use either blocked impurity band or bulk silicon devices. The switched FET readout scheme used on the three arrays flown thus far yields exceptionally low crosstalk. System sensitivities are found to be sufficient for the detection of both pointlike and extended sources; several of each type have been used in staring and scanning experiments.
Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.
Experimental device has low noise and high uniformity. Infrared imaging device combines array of InSb photodetectors with array of silicon field-effect-transistor switches. InSb chip forms roof over Si chip, each InSb detector cell engaging indium bump on corresponding Si switch cell below it. FET switches in 128-by-128 array turn on in sequence, read out charges on 128-by-128 array of photodetectors and multiplex them in serial output that represents pattern of light on array of photodetectors. Useful in sensitive infrared cameras for astronomy, medicine, inspection, and military surveillance. Reads out image data at rates up to 10 MHz and expands to 256-by-256 array.
The single event effects or phenomena (SEP), which so far have been observed as events falling on one or another of the SE classes: Single Event Upset (SEU), Single Event Latchup (SEL) and Single Event Burnout (SEB), are examined. Single event upset is defined as a lasting, reversible change in the state of a multistable (usually bistable) electronic circuit such as a flip-flop or latch. In a computer memory, SEUs manifest themselves as unexplained bit flips. Since latchup is in general caused by a single event of short duration, the single event part of the SEL term is superfluous. Nevertheless, it is used customarily to differentiate latchup due to a single heavy charged particle striking a sensitive cell from more ordinary kinds of latchup. Single event burnout (SEB) refers usually to total instantaneous failure of a power FET when struck by a single particle, with the device shorting out the power supply. An unforeseen failure of these kinds can be catastrophic to a space mission, and the possibilities are discussed.
The radar altimeter being developed for the Ocean Topography Experiment (TOPEX) will have an inherent instrument precision of 2 to 3 cm. While some minor refinements may be possible in the future, major geophysical advances could be made if altimetric measurements over a wide swath of the Earth's surface were possible. The NASA Headquarters Oceanic Processes Branch is supporting a 3-year investigation of the technological issues inherent in the precision measurement of topography from spaceborne platforms at angles off-nadir. To explore the off-nadir measurement of topography, a flexible, airborne radar instrument system is being developed. Its hardware design is now complete, and it is made up of several subsystems. The antenna selected is a dielectric lens of .894 m diameter. The RF subsystem uses phase-locked oscillators, FET solid-state amplifiers, and times four frequency multipliers to develop a transmit signal at a frequency of 36.0 GHz and a local oscillator signal at a frequency of 35.4 GHz. Lecroy 6880 digitizers under computer control digitize the five receiver outputs. The digital subsystem consists of six single-board Heurikon processors. At this time, the instrument construction continues with final system integration planned for November 1988.
Short-wavelength (1-2.5-micron) 128x128 focal plane arrays have been fabricated and demonstrated with high pixel yields and dark-current-limited performance. The detector material is HgCdTe grown by LPE on a sapphire substrate which yields high-performance uniform detectors. The detector arrays were characterized at temperatures of 80-150 K; the peak quantum efficiency at 2.4 microns is 80 percent. The multiplexer is a Reticon FET switch with output amplifiers. It is noted that the long-term goal of this project is to develop a 150x1000 mosaicked focal plane for use in the HIRIS instrument on the Earth Observing System.
GaAs circuits for use in a fully monolithic 1 Gb/s optical controller have been developed and tested. The circuits include photodetectors, transimpedance amplifiers and 1:16 demultiplexers that can directly control the phase of MMIC phase shifters. The entire chip contains approximately 300 self-aligned gate E/D-mode MESFETs. The MESFETs have one micron-wide gate and the E-mode FETs typically have transconductance of 200 ms/mm. Results of simulations and tests are reported. Also, the design and layout of the fully monolithic chip is discussed.
A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.
Advantages include reduced power and high speed. Experimental gallium arsenide field-effect-transistor (FET) domino circuit replicated in large numbers for use in dynamic-logic systems. Name of circuit denotes mode of operation, which logic signals propagate from each stage to next when successive stages operated at slightly staggered clock cycles, in manner reminiscent of dominoes falling in a row. Building block of domino circuit includes input, inverter, and level-shifting substages. Combinational logic executed in input substage. During low half of clock cycle, result of logic operation transmitted to following stage.