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At least 235 records · Page 13

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NASA NTRS2008

Fast Electromechanical Switches Based on Carbon Nanotubes

Electrostatically actuated nanoelectromechanical switches based on carbon nanotubes have been fabricated and tested in a continuing effort to develop high-speed switches for a variety of stationary and portable electronic equipment. As explained below, these devices offer advantages over electrostatically actuated microelectromechanical switches, which, heretofore, have represented the state of the art of rapid, highly miniaturized electromechanical switches. Potential applications for these devices include computer memories, cellular telephones, communication networks, scientific instrumentation, and general radiation-hard electronic equipment. A representative device of the present type includes a single-wall carbon nanotube suspended over a trench about 130 nm wide and 20 nm deep in an electrically insulating material. The ends of the carbon nanotube are connected to metal electrodes, denoted the source and drain electrodes. At bottom of the trench is another metal electrode, denoted the pull electrode (see figure). In the off or open switch state, no voltage is applied, and the nanotube remains out of contact with the pull electrode. When a sufficiently large electric potential (switching potential) is applied between the pull electrode and either or both of the source and drain electrodes, the resulting electrostatic attraction bends and stretches the nanotube into contact with the pull electrode, thereby putting the switch into the "on" or "closed" state, in which substantial current (typically as much as hundreds of nanoamperes) is conducted. Devices of this type for use in initial experiments were fabricated on a thermally oxidized Si wafer, onto which Nb was sputter-deposited for use as the pull-electrode layer. Nb was chosen because its refractory nature would enable it to withstand the chemical and thermal conditions to be subsequently imposed for growing carbon nanotubes. A 200- nm-thick layer of SiO2 was formed on top of the Nb layer by plasma-enhanced chemical vapor deposition. In the device regions, the SiO2 layer was patterned to thin it to the 20-nm trench depth. The trenches were then patterned by electron- beam lithography and formed by reactive- ion etching of the pattern through the 20-nm-thick SiO2 to the Nb layer.

Kaul, Anupama↗

DOE OSTI2024

Finding MIDDLE Ground: Scalable and Secure Distributed Learning

Edge computing methods allow devices to efficiently train a high-performing, robust, and personalized model for predictive tasks. However, these methods succumb to privacy and scalability concerns such as adversarial data recovery and expensive model communication. Furthermore, edge computing methods unrealistically assume that all devices train an identical model. In practice, edge devices have varying computational and memory constraints which may not allow certain devices to have the space or speed to train a specific model. To overcome these issues, we propose MIDDLE: a model independent distributed learning algorithm which allows heterogeneous edge devices to assist each other’s training while communicating only non-sensitive information. MIDDLE unlocks the ability for edge devices, regardless of computational or memory constraints, to assist each other even with completely different model architectures. Furthermore, MIDDLE does not require model or gradient communication which greatly reduces communication size and time. We prove that MIDDLE attains the optimal convergence rate O(1/sqrt(TM)) of stochastic gradient descent for convex and non-convex smooth optimization (for total iterations T and batch size M). Finally, our experimental results demonstrate that MIDDLE (even in non-IID data settings) attains robust and high-performing models without model or gradient communication.

Bornstein, Marc I.↗

NASA NTRS1978

The study of surface acoustic wave charge transfer device

A surface acoustic wave-charge transfer device, consisting of an n-type silicon substrate, a thermally grown silicon dioxide layer, and a sputtered film of piezoelectric zinc oxide is proposed as a means of circumventing problems associated with charge-coupled device (CCD) applications in memory, signal processing, and imaging. The proposed device creates traveling longitudinal electric fields in the silicon and replaces the multiphase clocks in CCD's. The traveling electric fields create potential wells which carry along charges stored there. These charges may be injected into the wells by light or by using a p-n junction as in conventional CCD's.

Papanicolaou, N.↗

NASA NTRS2008

Spaceborne Processor Array

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Chow, Edward T.↗

NASA NTRS1972

C-MOS array design techniques: SUMC multiprocessor system study

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

Clapp, W. A.↗

DOE OSTI2025

Quantum Imaging of Ferromagnetic van der Waals Magnetic Domain Structures at Ambient Conditions

Recently discovered 2D van der Waals magnetic materials, and specifically iron–germanium–telluride (Fe5GeTe2), have attracted significant attention both from a fundamental perspective and for potential applications. Key open questions concern their domain structure and magnetic phase transition temperature as a function of sample thickness and external field, as well as implications for integration into devices such as magnetic memories and logic. Here we address key questions using a nitrogen-vacancy center based quantum magnetic microscope, enabling direct imaging of the magnetization of Fe5GeTe2 at submicrometer spatial resolution as a function of temperature, magnetic field, and thickness. This quantum imaging technique provides noninvasive, high-sensitivity measurements with high spatial resolution under ambient conditions, making it particularly well suited for probing 2D magnets. We employ spatially resolved measures, including magnetization variance and cross-correlation, and find a significant spread in transition temperature yet with no clear dependence on thickness down to 15 nm. We also identify previously unknown stripe features in the optical as well as magnetic images, which we attribute to modulations of the constituting elements during crystal synthesis and subsequent oxidation. Our results suggest that the magnetic anisotropy in this material does not play a crucial role in their magnetic properties, leading to a magnetic phase transition of Fe5GeTe2 which is largely thickness-independent down to 15 nm. Our findings could be significant in designing future spintronic devices, magnetic memories, and logic with 2D van der Waals magnetic materials.

Bindu, Bindu [Hebrew University of Jerusalem, Isra↗

DOE OSTI2025

Automated Programmable Logic Controller Memory Forensics Using RGB Image Analysis and Deep Learning

The introduction of Industry 4.0 and Internet-based technologies has enhanced industrial control system operations but have inadvertently increased their vulnerabilities to cyber attacks. When an industrial control system is compromised, security analysts need to identify the root cause quickly to start the recovery process and develop mitigation strategies. Memory forensics is critical in the incident analysis process to ascertain what occurred. Approaches for analyzing the persistent memory in industrial control devices are limited and almost nonexistent for volatile memory. This chapter proposes an automated methodology for programmable logic controller memory dump analysis using computer vision and deep learning techniques. The methodology converts the sequences of bytes in a programmable logic controller memory dump to red-green-blue pixels and employs a deep learning model that learns the underlying patterns and features of pre-labeled forensic artifacts in images and segments them into distinct regions. The trained model is employed to automatically segment new memory images and identify forensic artifacts. Evaluation of the methodology on a Schneider Electric Modicon M221 programmable logic controller under code injection and code modification attacks demonstrates its ability to detect attack artifacts in memory dumps.

Asmar Awad, Rima [ORNL] (ORCID:0000000233407742)↗

NASA NTRS1994

Improved Ferroelectric Memories With Nondestructive Readout

Ferroelectric memories with enhanced photoresponse leading to improved nondestructive optoelectronic readout and lower power demand proposed. Memories improved versions of devices described in "Rapid, Nondestructive Readout From Ferroelectric Memory" (NPO-18551). In proposed application, array of nonvolatile ferroelectric memory cells fabricated by standard very-large-scale integrated-circuit techniques and flip-bonded onto similarly fabricated array of semiconductor lasers, {see "Optically Addressable, Ferroelectric Memory With NDRO" (NPO-18573)}.

Thakoor, Sarita↗

NASA NTRS1990

Solid-state reprogrammable analog resistive devices for electronic neural networks

The fabrication and performance of WO3-based, solid-state, three-terminal device configurations as programmable analog memory elements are reported. These transistorlike device structures exhibit good resistance progammability with a remarkable resolution of a few percent of the resistive strength over a four orders of magnitude dynamic range. The most critical component of these devices is an insulating layer between the active WO3 and the cation donor layer. The progamming characteristics and operation mechanisms of the device are described, and probable reaction mechanisms critical to the device stability are discussed.

Ramesham, R.↗

NASA NTRS1991

An electronic pan/tilt/zoom camera system

A camera system for omnidirectional image viewing applications that provides pan, tilt, zoom, and rotational orientation within a hemispherical field of view (FOV) using no moving parts was developed. The imaging device is based on the effect that from a fisheye lens, which produces a circular image of an entire hemispherical FOV, can be mathematically corrected using high speed electronic circuitry. An incoming fisheye image from any image acquisition source is captured in memory of the device, a transformation is performed for the viewing region of interest and viewing direction, and a corrected image is output as a video image signal for viewing, recording, or analysis. As a result, this device can accomplish the functions of pan, tilt, rotation, and zoom throughout a hemispherical FOV without the need for any mechanical mechanisms. A programmable transformation processor provides flexible control over viewing situations. Multiple images, each with different image magnifications and pan tilt rotation parameters, can be obtained from a single camera. The image transformation device can provide corrected images at frame rates compatible with RS-170 standard video equipment.

Zimmermann, Steve↗

NASA NTRS1999

Omniview motionless camera orientation system

A device for omnidirectional image viewing providing pan-and-tilt orientation, rotation, and magnification within a hemispherical field-of-view that utilizes no moving parts. The imaging device is based on the effect that the image from a fisheye lens, which produces a circular image of at entire hemispherical field-of-view, which can be mathematically corrected using high speed electronic circuitry. More specifically, an incoming fisheye image from any image acquisition source is captured in memory of the device, a transformation is performed for the viewing region of interest and viewing direction, and a corrected image is output as a video image signal for viewing, recording, or analysis. As a result, this device can accomplish the functions of pan, tilt, rotation, and zoom throughout a hemispherical field-of-view without the need for any mechanical mechanisms. The preferred embodiment of the image transformation device can provide corrected images at real-time rates, compatible with standard video equipment. The device can be used for any application where a conventional pan-and-tilt or orientation mechanism might be considered including inspection, monitoring, surveillance, and target acquisition.

Zimmermann, Steven D.↗

DOE OSTI2026

Ferroelectric Fractals: Switching Mechanism of Wurtzite AlN

The advent of wurtzite ferroelectrics is enabling new ferroelectric devices for computer memory that have the potential to bypass the von Neumann bottleneck due to their robust polarization and silicon compatibility. However, the atomistic switching mechanism of wurtzites is still undetermined due to the limitations of density functional theory simulation size and experimental temporal and spatial resolution. Thus, physics-informed materials engineering to reduce coercive field and breakdown in these devices has been limited. In this work, the atomistic mechanism of domain wall migration and domain growth in aluminum nitride-based wurtzites is uncovered using molecular dynamics and Monte Carlo simulations. We reveal the anomalous switching mechanism of fast 1D single columns of atoms propagating from a slow-moving 2D fractallike domain wall. We find that the critical nucleus is a single aluminum ion that breaks its bond with one nitrogen and bonds to another nitrogen; this creates a cascade that flips atoms directly only in the same column, due to the extreme locality (sharpness) of the domain walls in wurtzites. We further show how the fractallike shape of the domain wall in the 2D plane breaks assumptions in the Kolmogorov, Avrami, and Ishibashi (KAI) model and leads to the anomalously fast switching in wurtzite structured ferroelectrics.

36 MATERIALS SCIENCE↗

NASA NTRS1990

Rapid recovery from transient faults in the fault-tolerant processor with fault-tolerant shared memory

The Draper fault-tolerant processor with fault-tolerant shared memory (FTP/FTSM), which is designed to allow application tasks to continue execution during the memory alignment process, is described. Processor performance is not affected by memory alignment. In addition, the FTP/FTSM incorporates a hardware scrubber device to perform the memory alignment quickly during unused memory access cycles. The FTP/FTSM architecture is described, followed by an estimate of the time required for channel reintegration.

Harper, Richard E.↗

NASA NTRS1999

EXPRESS Rack Technology for Space Station

The EXPRESS rack provides accommodations for standard Mid-deck Locker and ISIS drawer payloads on the International Space Station. A design overview of the basic EXPRESS rack and two derivatives, the Human Research Facility and the Habitat Holding Rack, is given in Part I. In Part II, the design of the Solid State Power Control Module (SSPCM) is reviewed. The SSPCM is a programmable and remotely controllable power switching and voltage conversion unit which distributes and protects up to 3kW of 12OVDC and 28VDC power to payloads and rack subsystem components. Part III details the development and testing of a new data storage device, the BRP EXPRESS Memory Unit (BEMU). The BEMU is a conduction-cooled device which operates on 28VDC and is based on Boeing-modified 9GB commercial disk-drive technology. In Part IV results of a preliminary design effort for a rack Passive Damping System (PDS) are reported. The PDS is intended to isolate ISPR-based experiment racks from on-orbit vibration. System performance predictions based on component developmental testing indicate that such a system can provide effective isolation at frequencies of 1 Hz and above.

Davis, Ted B.↗

DOE OSTI2025

Extending SEER for Extreme Heterogeneity

Heterogeneous and multi-device nodes are increasingly common in high-performance computing and data centers, yet existing programming models often lack simple, transparent, and portable support for these diverse architectures. The main contribution of this work is the development of novel SEER capabilities to address this challenge by providing a descriptive programming model that allows applications to seamlessly leverage heterogeneous nodes across various device types. SEER uses efficient memory management and can select the proper device[s] depending on the computational cost of the applications. This is completely transparent to the programmer, thereby providing a highly productive programming environment. Integrating extreme heterogeneity into the SEER library as shown with the use of NVIDIA and AMD GPUs simultaneously allows it to expand and exploit the performance possibilities. Our analysis based on the well-known Conjugate Gradient algorithm reports accelerations above 1.5 × on computationally demanding steps of such an algorithm by using both architectures simultaneously.

Teranishi, Keita [ORNL] (ORCID:0000000166472690)↗

NASA NTRS2020

NASA Goddard Space Flight Center’s Compendium of Radiation Effects Test Results

Total ionizing dose, displacement damage dose, and single event effects testing were performed to characterize and determine the suitability of candidate electronics for NASA space utilization. Devices tested include FETs, flash memory, FPGAs, optoelectronics, digital, analog, and bipolar devices.

Single Event Effects (SEE)↗

NASA NTRS2020

NASA Goddard Space Flight Center’s Compendium of Radiation Effects Test Results

Single Event Effects (SEE)↗

DOE OSTI2025

Programmable Cryogenic Memory in a Ge/GeSi Heterostructure

Programmable memory components that operate optimally at cryogenic temperatures are essential for cryogenic computing architectures that seek to implement computing-in-memory. In this work, we demonstrate highly programmable memory in a Ge/GeSi heterostructure field-effect transistor (HFET). To operate, the HFET is gated to introduce positive carriers within the Ge quantum well, creating a high-conductance state. We show that this device can be set to a low-conductance state by sweeping a negative bias on the device drain, and reset it to its high-conductance state by sweeping a more positive bias on the device gate, thereby creating memory. We then determine that the device can be programmed within a 103 range of conductances using either the SET or the RESET operation. We propose that memory is achieved through charge trapping as carriers tunnel out of the quantum well, and that altering the density and spatial distribution of carriers modulates the device conductance. This mechanism exhibits endurance over 1000 cycles at temperatures ≤ 25 K, suggesting that the carrier traps are located at the oxide-semiconductor interface. As a first demonstration of programmable conductance in a Ge/GeSi HFET, this work highlights the potential of group-IV HFETs to perform as analog cryogenic memory components.

cryogenic memory↗