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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

Bell, L. D.↗
NASA NTRS2008

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

LaBel, Kenneth A.↗
NASA NTRS1990

Solid-state thin-film memistor for electronic neural networks

This paper reports on a tungsten-oxide-based, nonvolatile, electrically reprogrammable, variable resistance device as an analog synaptic memory connection for electronic neural networks. A voltage controlled, reversible injection of H(+) ions in electrochromic thin films of WO3 is utilized to modulate its resistance. A hygroscopic thin film of Cr2O3 is the source of H(+) ions. The resistance of the device can be tailored and stabilized over a wide dynamic range (about 4 orders of magnitude), and the programming speed is modulated by the control voltage. The suitability of such a device in terms of its response speed, reversibility, stability, and cyclability for its use in electronic neural networks is discussed.

Thakoor, S.↗
NASA NTRS1987

Hybrid analog-digital associative neural network

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of the second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

Moopenn, Alexander W.↗
NASA NTRS1989

Hybrid analog-digital associative neural network

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

Moopenn, Alexander W.↗
NASA NTRS2001

A radiation - tolerant, low - power non - volatile memory based on silicon nanocrystal quantum dots.

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in Si02 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled.

Green, M. L.↗
NASA NTRS1985

Feasibility of self-structured current accessed bubble devices in spacecraft recording systems

The self-structured, current aperture approach to magnetic bubble memory is described. Key results include: (1) demonstration that self-structured bubbles (a lattice of strongly interacting bubbles) will slip by one another in a storage loop at spacings of 2.5 bubble diameters, (2) the ability of self-structured bubbles to move past international fabrication defects (missing apertures) in the propagation conductors (defeat tolerance), and (3) moving bubbles at mobility limited speeds. Milled barriers in the epitaxial garnet are discussed for containment of the bubble lattice. Experimental work on input/output tracks, storage loops, gates, generators, and magneto-resistive detectors for a prototype device are discussed. Potential final device architectures are described with modeling of power consumption, data rates, and access times. Appendices compare the self-structured bubble memory from the device and system perspectives with other non-volatile memory technologies.

Nelson, G. L.↗
NASA NTRS2015

Shape Memory Alloy Rock Splitters (SMARS) - A Non-Explosive Method for Fracturing Planetary Rocklike Materials and Minerals

A static rock splitter device based on high-force, high-temperature shape memory alloys (HTSMAs) was developed for space related applications requiring controlled geologic excavation in planetary bodies such as the Moon, Mars, and near-Earth asteroids. The device, hereafter referred to as the shape memory alloy rock splitter (SMARS), consisted of active (expanding) elements made of Ni50.3Ti29.7Hf20 (at.%) that generate extremely large forces in response to thermal input. The preshaping (training) of these elements was accomplished using isothermal, isobaric and cyclic training methods, which resulted in active components capable of generating stresses in excess of 1.5 GPa. The corresponding strains (or displacements) were also evaluated and were found to be 2 to 3 percent, essential to rock fracturing and/or splitting when placed in a borehole. SMARS performance was evaluated using a test bed consisting of a temperature controller, custom heaters and heater holders, and an enclosure for rock placement and breakage. The SMARS system was evaluated using various rock types including igneous rocks (e.g., basalt, quartz, granite) and sedimentary rocks (e.g., sandstone, limestone).

NiTiHf↗
NASA NTRS1991

Formal verification of an MMU and MMU cache

We describe the formal verification of a hardware subsystem consisting of a memory management unit and a cache. These devices are verified independently and then shown to interact correctly when composed. The MMU authorizes memory requests and translates virtual addresses to real addresses. The cache improves performance by maintaining a LRU (least recently used) list from the memory resident segment table.

Schubert, E. T.↗
NASA NTRS2008

Carbon nanotube switches for memory, RF communications and sensing applications, and methods of making the same

Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to elecrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers.

Kaul, Anupama B.↗
NASA NTRS1979

Implementing a bubble memory hierarchy system

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

Segura, R.↗
NASA NTRS1987

Gigarad-tolerant power switches and memory elements

A new class of silicon devices operating without p-n junctions has been studied for radiation hardness. The electric field in these devices is uniform over most of the device, thus causing high-voltage breakdown to increase with electrode spacing. Deep acceptor levels are created in the silicon by diffusing gold atoms into the lattice, or by electron radiation. These acceptor levels, near the center of the band gap, trap out electrons so that the low resistivity of the n-type doped wafer can be raised to intrinsic resistivity. Switching between a high-resistivity state at low currents and a low-resistivity state at high currents occurs at a definite threshold voltage, exhibiting characteristics similar to silicon-controlled rectifiers. Compensating 0.1 ohm-meter (10 ohm-cm) silicon wafers requires electron fluxes of 10 to the 23rd electrons per square meter (10 to the 19th electrons per square centimeter). Experiments demonstrating gamma tolerance to 1 Gigarad(Si) are described. Calculations for maximum tolerable neutron fluence are shown, and a phenomenological explanation for these results is presented.

Joyner, W. T.↗
NASA NTRS1985

Advances in rechargeable lithium molybdenum disulfide batteries

The lithium molybdenum disulfide system as demonstrated in a C size cell, offers performance characteristics for applications where light weight and low volume are important. A gravimetric energy density of 90 watt hours per kilogram can be achieved in a C size cell package. The combination of charge retention capabilities, high energy density and a state of charge indicator in a rechargeable cell provides power package for a wide range of devices. The system overcomes the memory effect in Nicads where the full capacity of the battery cannot be utilized unless it was utilized on previous cycles. The development of cells with an advanced electrolyte formulation led to an improved rate capability especially at low temperatures and to a significantly improved life cycle.

Brandt, K.↗
NASA NTRS1985

Computers in Aerospace Conference, 5th, Long Beach, CA, October 21-23, 1985, Technical Papers

Among the topics discussed are: access control models for a distributed CAIS-conforming system; a knowledge-based advisory system for casualty procedures; and automated interactive simulation modeling system. Consideration is also given to: reusable software concepts and software development methodologies; the electronic device aspects of neutral network memories; an expert system for automated satellite anomaly resolution; and the use of automatic programming techniques for fault-tolerant computing systems. Among additional topics discussed are: systems approaches to software fault tolerance; a Space Shuttle navigation validation system; and a vision-based road following system for an autonomous land vehicle.

Source record↗
NASA NTRS1990

Temperature Dependence Of Single-Event Effects

Report describes experimental study of effects of temperature on vulnerability of integrated-circuit memories and other electronic logic devices to single-event effects - spurious bit flips or latch-up in logic state caused by impacts of energetic ions. Involved analysis of data on 14 different device types. In most cases examined, vulnerability to these effects increased or remain constant with temperature.

Coss, James R.↗
NASA NTRS1992

Coupling device with improved thermal interface

The primary object of the present invention is to provide a simple, reliable, and lightweight coupling that will also have an efficient thermal interface. A further object of the invention is to provide a coupling that is capable of blind mating with little or no insertion forces. Another object of the invention is to provide a coupling that acts as a thermal regulator to maintain a constant temperature on one side of the coupling. Another object of the invention is to increase the available surface area of a coupling thus providing a larger area for the conduction of heat across the thermal interface. Another object of the invention is to provide a fluidic coupling that has no fluid passing across the interface, thus reducing the likelihood of leaks and contamination. The foregoing objects are achieved by utilizing, as in the prior art, a hot area (at an elevated temperature as compared to a cold area) with a need to remove excess heat from the hot area to a cold area. In this device, the thermal interface will occur not on a planar horizontal surface, but along a non-planar vertical surface, which will reduce the reaction forces and increase the thermal conductivity of the device. One non-planar surface is a surface on a cold pin extending from the cold area and the other non-planar surface is a surface on a hot pin extending from the hot area. The cold pin is fixed and does not move while the hot pin is a flexible member and its movement towards the cold pin will bring the two non-planar surfaces together forming the thermal interface. The actuating member for the device is a shape-memory actuation wire which is attached through an aperture to the hot pin and through another aperture to an actuation wire retainer. By properly programming the actuation wire, heat from the hot area will cause the actuation wire to bend the hot wire. Heat from the hot area will cause the actuation wire to bend the hot pin towards the cold pin forming the coupling and the desired thermal interface. The shape-memory actuation wire is made of a shape-memory-effect alloy such as Nitinol.

Milam, Malcolm Bruce↗
NASA NTRS2005

Reconfigurable Processing Module

To accommodate a wide spectrum of applications and technologies, NASA s Exploration System's Missions Directorate has called for reconfigurable and modular technologies to support future missions to the moon and Mars. In response, Langley Research Center is leading a program entitled Reconfigurable Scaleable Computing (RSC) that is centered on the development of FPGA-based computing resources in a stackable form factor. This paper details the architecture and implementation of the Reconfigurable Processing Module (RPM), which is the key element of the RSC system. The RPM is an FPGA-based, space-qualified printed circuit assembly leveraging terrestrial/commercial design standards into the space applications domain. The form factor is similar to, and backwards compatible with, the PCI-104 standard utilizing only the PCI interface. The size is expanded to accommodate the required functionality while still better than 30% smaller than a 3U CompactPCI(TradeMark)card and without the overhead of the backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission application resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via the PCI bus to onboard SDRAM, flash PROM, and the application resources; both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as the Application FPGA - or simply "the application" - is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom application specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of the reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore the performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.

Somervill, Kevin↗