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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS1990

Evaluation of the Trajectory Operations Applications Software Task (TOAST)

The Trajectory Operations Applications Software Task (TOAST) is a software development project under the auspices of the Mission Operations Directorate. Its purpose is to provide trajectory operation pre-mission and real-time support for the Space Shuttle program. As an Application Manager, TOAST provides an isolation layer between the underlying Unix operating system and the series of user programs. It provides two main services: a common interface to operating system functions with semantics appropriate for C or FORTRAN, and a structured input and output package that can be utilized by user application programs. In order to evaluate TOAST as an Application Manager, the task was to assess current and planned capabilities, compare capabilities to functions available in commercially-available off the shelf (COTS) and Flight Analysis Design System (FADS) users for TOAST implementation. As a result of the investigation, it was found that the current version of TOAST is well implemented and meets the needs of the real-time users. The plans for migrating TOAST to the X Window System are essentially sound; the Executive will port with minor changes, while Menu Handler will require a total rewrite. A series of recommendations for future TOAST directions are included.

Perkins, Sharon↗
NASA NTRSDate not supplied

Gateway Program Development Progress

This paper provides an overview and status of Gateway, humanity’s first space station to orbit the Moon providing vital support for a sustained, long-term human return to the lunar surface and a steppingstone to Mars as part of the Artemis missions. As a lunar outpost, Gateway is a destination for deep space crew expeditions and science investigations, a port for deep space transportation, including landers transiting to the lunar surface or spacecraft embarking to deep space destinations beyond the Earth-Moon system. The National Aeronautics and Space Administration (NASA) leads the Program and is the integrator of the spaceflight capabilities and contributions of U.S. commercial partners and international partners to develop Gateway. This paper will provide an overview of Gateway’s major components in various stages of development. The entire Gateway spacecraft is at preliminary design level of maturity, with some components at or near critical design review. Gateway’s major components are the Power and Propulsion Element; the Habitation and Logistics Outpost; Deep Space Logistics; the International Habitation module; Gateway External Robotics System; European System Providing Refueling, Infrastructure and Telecommunications; and an Airlock. This paper will also provide an update on the status of the integration activities necessary to fly and operate this complex, next-generation integrated spacecraft for a minimum 15 year design life, including systems engineering integrated analysis cycles, the autonomous Vehicle System Manager software, verification and validation labs, and common vehicle equipment. Expanding on the successful partnership that has provided over 20 years of continuous crew operations in low-Earth orbit on the International Space Station, Gateway is an evolution of this extraordinary partnership leveraging the capabilities of each contributor to expand humankind’s sustained exploration deeper into the cosmos. Highlighting the international program with participation from multiple space agencies, this paper will also provide a status of Gateway multilateral governance structure and international agreements.

Sean M Fuller↗
NASA NTRS2024

Gateway Program Development Progress

This paper provides an overview and status of Gateway, humanity’s first space station to orbit the Moon providing vital support for a sustained, long-term human return to the lunar surface and a steppingstone to Mars as part of the Artemis missions. As a lunar outpost, Gateway is a destination for deep space crew expeditions and science investigations, a port for deep space transportation, including landers transiting to the lunar surface or spacecraft embarking to deep space destinations beyond the Earth-Moon system. The National Aeronautics and Space Administration (NASA) leads the Program and is the integrator of the spaceflight capabilities and contributions of U.S. commercial partners and international partners to develop Gateway. This paper will provide an overview of Gateway’s major components in various stages of development. The entire Gateway spacecraft is at preliminary design level of maturity, with some components at or near critical design review. Gateway’s major components are the Power and Propulsion Element; the Habitation and Logistics Outpost; Deep Space Logistics; the International Habitation module; Gateway External Robotics System; European System Providing Refueling, Infrastructure and Telecommunications; and an Airlock. This paper will also provide an update on the status of the integration activities necessary to fly and operate this complex, next-generation integrated spacecraft for a minimum 15-year design life, including systems engineering integrated analysis cycles, the autonomous Vehicle System Manager software, verification and validation labs, and common vehicle equipment. Expanding on the successful partnership that has provided over 20 years of continuous crew operations in low-Earth orbit on the International Space Station, Gateway is an evolution of this extraordinary partnership leveraging the capabilities of each contributor to expand humankind’s sustained exploration deeper into the cosmos. Highlighting the international program with participation from multiple space agencies, this paper will also provide a status of Gateway multilateral governance structure and international agreements.

Gateway↗
NASA NTRS1995

The scheme machine: A case study in progress in design derivation at system levels

The Scheme Machine is one of several design projects of the Digital Design Derivation group at Indiana University. It differs from the other projects in its focus on issues of system design and its connection to surrounding research in programming language semantics, compiler construction, and programming methodology underway at Indiana and elsewhere. The genesis of the project dates to the early 1980's, when digital design derivation research branched from the surrounding research effort in programming languages. Both branches have continued to develop in parallel, with this particular project serving as a bridge. However, by 1990 there remained little real interaction between the branches and recently we have undertaken to reintegrate them. On the software side, researchers have refined a mathematically rigorous (but not mechanized) treatment starting with the fully abstract semantic definition of Scheme and resulting in an efficient implementation consisting of a compiler and virtual machine model, the latter typically realized with a general purpose microprocessor. The derivation includes a number of sophisticated factorizations and representations and is also deep example of the underlying engineering methodology. The hardware research has created a mechanized algebra supporting the tedious and massive transformations often seen at lower levels of design. This work has progressed to the point that large scale devices, such as processors, can be derived from first-order finite state machine specifications. This is roughly where the language oriented research stops; thus, together, the two efforts establish a thread from the highest levels of abstract specification to detailed digital implementation. The Scheme Machine project challenges hardware derivation research in several ways, although the individual components of the system are of a similar scale to those we have worked with before. The machine has a custom dual-ported memory to support garbage collection. It consists of four tightly coupled processes--processor, collector, allocator, memory--with a very non-trivial synchronization relationship. Finally, there are deep issues of representation for the run-time objects of a symbolic processing language. The research centers on verification through integrated formal reasoning systems, but is also involved with modeling and prototyping environments. Since the derivation algebra is basd on an executable modeling language, there is opportunity to incorporate design animation in the design process. We are looking for ways to move smoothly and incrementally from executable specifications into hardware realization. For example, we can run the garbage collector specification, a Scheme program, directly against the physical memory prototype, and similarly, the instruction processor model against the heap implementation.

Johnson, Steven D.↗
NASA NTRS2000

Use Computer-Aided Tools to Parallelize Large CFD Applications

Porting applications to high performance parallel computers is always a challenging task. It is time consuming and costly. With rapid progressing in hardware architectures and increasing complexity of real applications in recent years, the problem becomes even more sever. Today, scalability and high performance are mostly involving handwritten parallel programs using message-passing libraries (e.g. MPI). However, this process is very difficult and often error-prone. The recent reemergence of shared memory parallel (SMP) architectures, such as the cache coherent Non-Uniform Memory Access (ccNUMA) architecture used in the SGI Origin 2000, show good prospects for scaling beyond hundreds of processors. Programming on an SMP is simplified by working in a globally accessible address space. The user can supply compiler directives, such as OpenMP, to parallelize the code. As an industry standard for portable implementation of parallel programs for SMPs, OpenMP is a set of compiler directives and callable runtime library routines that extend Fortran, C and C++ to express shared memory parallelism. It promises an incremental path for parallel conversion of existing software, as well as scalability and performance for a complete rewrite or an entirely new development. Perhaps the main disadvantage of programming with directives is that inserted directives may not necessarily enhance performance. In the worst cases, it can create erroneous results. While vendors have provided tools to perform error-checking and profiling, automation in directive insertion is very limited and often failed on large programs, primarily due to the lack of a thorough enough data dependence analysis. To overcome the deficiency, we have developed a toolkit, CAPO, to automatically insert OpenMP directives in Fortran programs and apply certain degrees of optimization. CAPO is aimed at taking advantage of detailed inter-procedural dependence analysis provided by CAPTools, developed by the University of Greenwich, to reduce potential errors made by users. Earlier tests on NAS Benchmarks and ARC3D have demonstrated good success of this tool. In this study, we have applied CAPO to parallelize three large applications in the area of computational fluid dynamics (CFD): OVERFLOW, TLNS3D and INS3D. These codes are widely used for solving Navier-Stokes equations with complicated boundary conditions and turbulence model in multiple zones. Each one comprises of from 50K to 1,00k lines of FORTRAN77. As an example, CAPO took 77 hours to complete the data dependence analysis of OVERFLOW on a workstation (SGI, 175MHz, R10K processor). A fair amount of effort was spent on correcting false dependencies due to lack of necessary knowledge during the analysis. Even so, CAPO provides an easy way for user to interact with the parallelization process. The OpenMP version was generated within a day after the analysis was completed. Due to sequential algorithms involved, code sections in TLNS3D and INS3D need to be restructured by hand to produce more efficient parallel codes. An included figure shows preliminary test results of the generated OVERFLOW with several test cases in single zone. The MPI data points for the small test case were taken from a handcoded MPI version. As we can see, CAPO's version has achieved 18 fold speed up on 32 nodes of the SGI O2K. For the small test case, it outperformed the MPI version. These results are very encouraging, but further work is needed. For example, although CAPO attempts to place directives on the outer- most parallel loops in an interprocedural framework, it does not insert directives based on the best manual strategy. In particular, it lacks the support of parallelization at the multi-zone level. Future work will emphasize on the development of methodology to work in a multi-zone level and with a hybrid approach. Development of tools to perform more complicated code transformation is also needed.

Jin, H.↗
NASA NTRS2004

Space Network Devices Developed

The NASA Glenn Research Center through a contract with Spectrum Astro, Inc., has been developing space network hardware as an enabling technology using open systems interconnect (OSI) standards for space-based communications applications. The OSI standard is a well-recognized layered reference model that specifies how data should be sent node to node in a communications network. Because of this research and technology development, a space-qualifiable Ethernet-based network interface card (similar to the type found in a networked personal computer) and the associated four-port hub were designed and developed to flight specifications. During this research and development, there also have been many lessons learned for determining approaches for migrating existing spacecraft architectures to an OSI-network-based platform. Industry has recognized the benefits of targeting hardware developed around OSI standards such as Transmission Control Protocol/Internet Protocol (TCP/IP) or similar protocols for use in future generations of space communication systems. Some of these tangible benefits include overall reductions in mission schedule and cost and in system complexity. This development also brings us a step closer to the realization of a principal investigator on a terrestrial Internet site being able to interact with space platform assets in near real time. To develop this hardware, Spectrum Astro first conducted a technology analysis of alternatives study. For this analysis, they looked at the features of three protocol specifications: Ethernet (IEEE 802.3), Firewire (IEEE 1394), and Spacewire (IEEE 1355). A thorough analysis was performed on the basis of criteria such as current protocol performance and suitability for future space applications. Spectrum Astro also projected future influences such as cost, hardware and software availability, throughput performance, and integration procedures for current and transitive space architectures. After a thorough analysis, Ethernet was chosen because it was seen as the best longer term fit because of the prevalent commercial market; the current and projected availability of hardware, software, and development tools; and the ease of architecture integration.

Jones, Robert E.↗
NASA NTRSDate not supplied

Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits

A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.

DC Powered Oven↗
NASA NTRSDate not supplied

FUN3D Analyses in Support of the 1st AIAA Stability and Control Prediction Workshop

The 1st AIAA Stability and Control Prediction Workshop was created to establish best practices for the prediction of stability & control derivatives using computational fluid dynamics and assess the limitations of these computational methods when those best practices are applied. The inaugural workshop considers the ONERA version of the NASA/Boeing Common Research Model(CRM), which includes the wing, body, horizontal tail, and a vertical tail designed by ONERA. Wind tunnel tests have been conducted for this configuration with longitudinal tests having been previously published, in addition to unpublished data at small sideslip angles that will serve as ‘blind’ data for workshop data comparisons. Participants were provided a ‘family’ of unstructured grids for the full-span ONERA CRM model with the wind-tunnel sting included. This family of mixed-element grids consists of 5 levels of refinement (tiny, coarse, medium, fine, and extra fine) with surface and volume mesh scaling, resulting in a size range of 14.6 to 53.4 million nodes. In addition, a medium refinement mesh has been provided for the ONERA CRM configuration without a sting to evaluate the sting’s impact on static longitudinal stability characteristics. In addition to these workshop-provided grids, the present work also considers an equivalent ‘family’ of computational grids generated using Heldenmesh™, a rapid grid generation software by Helden Aerospace Corporation for creating high-quality, three-dimensional, mixed-element unstructured meshes. Because of the authors’ familiarity with this software, these additional grids were generated as a comparison to the workshop-provided grids and to better understand the implications of using volume-mirrored grids for stability and control predictions. The present work will contribute to the workshop with test case data generated using the NASA FUN3D code, a parallelized, unstructured, node-based, finite-volume discretization, Reynolds-averaged Navier-Stokes flow solver. Numerical simulations will be conducted using the Quadratic Constitutive Relationship (QCR) version of the Spalart-Allmaras (SA) turbulence model with negative turbulence variable provisions. Both steady and2nd-order, time-accurate simulation results are to be generated and compared for select test cases, as time permits, to investigate their impact on FUN3D predictions. The present work will consider the three primary workshop test cases: (1) grid convergence study, (2) Mach number effect on static stability, and (3) wind tunnel sting increments. Additionally, data will be provided for the two optional test cases, which include:(1) static stability derivative calculations and (2)sideslip angle sweeps. In each of the test cases, the vehicle is stationary, and the body is assumed to be rigid, where vehicle deformation has been accounted for in the model configuration geometry. For all test cases, longitudinal and lateral force and moment aerodynamic coefficients will be provided for the total configuration, in addition to a component-level breakdown that includes the port wing, starboard wing, fuselage, and tail.

CFD↗
NASA NTRS2006

Promoted-Combustion Chamber with Induction Heating Coil

An improved promoted-combustion system has been developed for studying the effects of elevated temperatures on the flammability of metals in pure oxygen. In prior promoted-combustion chambers, initial temperatures of metal specimens in experiments have been limited to the temperatures of gas supplies, usually near room temperature. Although limited elevated temperature promoted-combustion chambers have been developed using water-cooled induction coils for preheating specimens, these designs have been limited to low-pressure operation due to the hollow induction coil. In contrast, the improved promoted-combustion chamber can sustain a pressure up to 10 kpsi (69 MPa) and, through utilization of a solid induction coil, is capable of preheating a metal specimen up to its melting point [potentially in excess of 2,000 F (approximately equal to 1,100 C)]. Hence, the improved promoted combustion chamber makes a greater range of physical conditions and material properties accessible for experimentation. The chamber consists of a vertical cylindrical housing with an inner diameter of 8 in. (20.32 cm) and an inner height of 20.4 in. (51.81 cm). A threaded, sealing cover at one end of the housing can be unscrewed to gain access for installing a specimen. Inlet and outlet ports for gases are provided. Six openings arranged in a helical pattern in the chamber wall contain sealed sapphire windows for viewing an experiment in progress. The base of the chamber contains pressure-sealed electrical connectors for supplying power to the induction coil. The connectors feature a unique design that prevents induction heating of the housing and the pressure sealing surfaces; this is important because if such spurious induction heating were allowed to occur, chamber pressure could be lost. The induction coil is 10 in. (25.4 cm) long and is fitted with a specimen holder at its upper end. At its lower end, the induction coil is mounted on a ceramic base, which affords thermal insulation to prevent heating of the base of the chamber during use. A sapphire cylinder protects the coil against slag generated during an experiment. The induction coil is energized by a 6-kW water-cooled power supply operating at a frequency of 400 kHz. The induction coil is part of a parallel-tuned circuit, the tuning of which is used to adjust the coupling of power to the specimen. The chamber is mounted on a test stand along with pumps, valves, and plumbing for transferring pressurized gas into and out of the chamber. In addition to multiple video cameras aimed through the windows encircling the chamber, the chamber is instrumented with gauges for monitoring the progress of an experiment. One of the gauges is a dual-frequency infrared temperature transducer aimed at the specimen through one window. Chamber operation is achieved via a console that contains a computer running apparatus-specific software, a video recorder, and real-time video monitors. For safety, a blast wall separates the console from the test stand.

Richardson, Erin↗
NASA NTRS1993

A SIMULINK environment for flight dynamics and control analysis: Application to the DHC-2 Beaver. Part 1: Implementation of a model library in SIMULINK. Part 2: Nonlinear analysis of the Beaver autopilot

The design of advanced Automatic Aircraft Control Systems (AACS's) can be improved upon considerably if the designer can access all models and tools required for control system design and analysis through a graphical user-interface, from within one software environment. This MSc-thesis presents the first step in the development of such an environment, which is currently being done at the Section for Stability and Control of Delft University of Technology, Faculty of Aerospace Engineering. The environment is implemented within the commercially available software package MATLAB/SIMULINK. The report consists of two parts. Part I gives a detailed description of the AACS design environment. The heart of this environment is formed by the SIMULINK implementation of a nonlinear aircraft model in block-diagram format. The model has been worked out for the old laboratory aircraft of the Faculty, the De Havilland DHC-2 'Beaver', but due to its modular structure, it can easily be adapted for other aircraft. Part I also describes MATLAB programs which can be applied for finding steady-state trimmed-flight conditions and for linearization of the aircraft model, and it shows how the built-in simulation routines of SIMULINK have been used for open-loop analysis of the aircraft dynamics. Apart from the implementation of the models and tools, a thorough treatment of the theoretical backgrounds is presented. Part II of this report presents a part of an autopilot design process for the 'Beaver' aircraft, which clearly demonstrates the power and flexibility of the AACS design environment from part I. Evaluations of all longitudinal and lateral control laws by means of nonlinear simulations are treated in detail. The AACS design environment from part I proved to be a very useful tool for designing the control laws of the 'Beaver' autopilot within a very tight time-schedule. The autopilot design process itself will be used as a guideline for future AACS research at the Faculty of Aerospace Engineering. Flight tests of the 'Beaver' autopilot, done after evaluating the control laws in the SIMULINK package, proved to be quite successful. In the future, the AACS design package will evolve into a standardized, integrated design environment which can be applied to virtually any type of aircraft. The AACS design cycle will be shortened further by developing tools for automatically porting control laws from the MATLAB/SIMULINK environment to a piloted real-time flight simulator and the Flight Control Computers of the aircraft.

Flight Control System Design↗
DOE OSTI2024

Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAs

There has been considerable interest and resulting progress in implementing machine learning (ML) models in hardware over the last several years from the particle and nuclear physics communities. A big driver has been the release of the Python package, hls4ml, which has enabled porting models specified and trained using Python ML libraries to register transfer level (RTL) code. So far, the primary end targets have been commercial field-programmable gate arrays (FPGAs) or synthesized custom blocks on application specific integrated circuits (ASICs). However, recent developments in open-source embedded FPGA (eFPGA) frameworks now provide an alternate, more flexible pathway for implementing ML models in hardware. These customized eFPGA fabrics can be integrated as part of an overall chip design. In general, the decision between a fully custom, eFPGA, or commercial FPGA ML implementation will depend on the details of the end-use application. In this work, we explored the parameter space for eFPGA implementations of fully-connected neural network (fcNN) and boosted decision tree (BDT) models using the task of neutron/gamma classification with a specific focus on resource efficiency. We used data collected using an AmBe sealed source incident on Stilbene, which was optically coupled to an OnSemi J-series silicon photomultiplier (SiPM) to generate training and test data for this study. We investigated relevant input features and the effects of bit-resolution and sampling rate as well as trade-offs in hyperparameters for both ML architectures while tracking total resource usage. The performance metric used to track model performance was the calculated neutron efficiency at a gamma leakage of 10 -3 . The results of the study will be used to aid the specification of an eFPGA fabric, which will be integrated as part of a test chip.

47 OTHER INSTRUMENTATION↗
NASA NTRS2004

Advanced Signal Conditioners for Data-Acquisition Systems

Signal conditioners embodying advanced concepts in analog and digital electronic circuitry and software have been developed for use in data-acquisition systems that are required to be compact and lightweight, to utilize electric energy efficiently, and to operate with high reliability, high accuracy, and high power efficiency, without intervention by human technicians. These signal conditioners were originally intended for use aboard spacecraft. There are also numerous potential terrestrial uses - especially in the fields of aeronautics and medicine, wherein it is necessary to monitor critical functions. Going beyond the usual analog and digital signal-processing functions of prior signal conditioners, the new signal conditioner performs the following additional functions: It continuously diagnoses its own electronic circuitry, so that it can detect failures and repair itself (as described below) within seconds. It continuously calibrates itself on the basis of a highly accurate and stable voltage reference, so that it can continue to generate accurate measurement data, even under extreme environmental conditions. It repairs itself in the sense that it contains a micro-controller that reroutes signals among redundant components as needed to maintain the ability to perform accurate and stable measurements. It detects deterioration of components, predicts future failures, and/or detects imminent failures by means of a real-time analysis in which, among other things, data on its present state are continuously compared with locally stored historical data. It minimizes unnecessary consumption of electric energy. The design architecture divides the signal conditioner into three main sections: an analog signal section, a digital module, and a power-management section. The design of the analog signal section does not follow the traditional approach of ensuring reliability through total redundancy of hardware: Instead, following an approach called spare parts tool box, the reliability of each component is assessed in terms of such considerations as risks of damage, mean times between failures, and the effects of certain failures on the performance of the signal conditioner as a whole system. Then, fewer or more spares are assigned for each affected component, pursuant to the results of this analysis, in order to obtain the required degree of reliability of the signal conditioner as a whole system. The digital module comprises one or more processors and field-programmable gate arrays, the number of each depending on the results of the aforementioned analysis. The digital module provides redundant control, monitoring, and processing of several analog signals. It is designed to minimize unnecessary consumption of electric energy, including, when possible, going into a low-power "sleep" mode that is implemented in firmware. The digital module communicates with external equipment via a personal-computer serial port. The digital module monitors the "health" of the rest of the signal conditioner by processing defined measurements and/or trends. It automatically makes adjustments to respond to channel failures, compensate for effects of temperature, and maintain calibration.

Lucena, Angel↗