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At least 235 records · Page 13

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DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front- end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high-speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel. Another novel low-power circuit called Pseudo-Thyristor presented in another document will replace traditional discriminator and the Regenerative Current Mirror plus Pseudo- Thyristor will provide a full solution for the silicon pixel low-power frontend ASIC.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS1977

Twin-capacitive shaft angle encoder with analog output signal

A precision capacitive shaft encoder providing a dc signal corresponding to the angular position of a shaft is described. Two variable capacitances are coupled in tandem by a rotatable shaft. Each capacitor has a capacitance that varies linearly with a change in the angular position of the shaft. The sum of the two capacitances is always constant for any angular position of the shaft. Each capacitance is alternately coupled to a reference dc voltage and a discharge circuit. The capacitances are electrically coupled in series and the charge periodically acquired at the junction of the capacitance is a function of the position of the shaft. An error-compensating voltage is imposed on the junction when the capacitances are coupled to the reference voltages. The junction is coupled to sample-and-hold apparatus provided with a error-correcting circuit.

Hruby, R. J.↗

DOE OSTI2023

Modifying Surface Chemistry to Enhance the Electrochemical Stability of Nickel‐Rich Cathode Materials

Residual impurities such as lithium carbonate and hydroxide are a major concern for accelerating parasitic reactions at the cathode electrolyte interface of lithium-ion batteries. Removal of these lithium-bearing species becomes a necessity for high-performance nickel-rich cathode materials. Instead of directly removing these impurities through washing steps, a wet impregnation process is employed to convert these detrimental surface impurities into beneficial surface coating on nickel-rich cathode materials. Specifically, the pristine cathode material is treated with Al(H 2 PO 4 ) 3 solution to convert undesired compounds into Li 3 PO 4 and AlPO 4 , both of which are considered positive surface coating materials for high-voltage cathodes. It is found that the introduced modification greatly suppresses the interfacial impedance hike and improves the capacity retention of the cathode material after repeating charging/discharging. It is believed that these benefits are realized through the modification of the surface chemistry of the cathode material, which helps to slow down the parasitic reactions and reduce the damage to the cathode material.

25 ENERGY STORAGE↗

DOE OSTI2023

Logical Majorana zero modes in a nanowire network

We present a scheme to use physical Majorana quasizero modes at each junction of a two-dimensional nanowire network to build a logical Majorana zero mode, the location of which is controllable through gate voltages. The wire network is a way to realize a recent proposal to imprint a Kekulé vortex pattern on a honeycomb lattice via gate voltages. We show that a specific type of junction, other than a naive Y or T junction, is needed to realize, without breaking time-reversal symmetry, an artificial “graphene” system with Majorana fermions instead of complex ones at each site. The junction we propose (i) traps exactly one physical Majorana (quasi)zero mode at each site of either a brick wall or honeycomb lattice and (ii) allows this mode to hybridize with all three neighboring sites. Using a lattice of these junctions and starting from an electronic, tight-binding model for the wires, we imprint the voltage patterns corresponding to the Kekulé vortex and observe the emergence of the logical Majorana zero mode at the vortex core. By suitable adiabatic modulations of gate voltages as a function of time, the positions of individual Kekulé vortices can be moved, and in this manner, non-Abelian braiding of the logical Majoranas bound to the vortex cores can be performed. We provide the range of parameters where these excitations could be realized experimentally.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2021

Photovoltaics Research and Development: Device Architecture for Next-Generation CdTe PV. Cooperative Research and Development Final Report, CRADA Number CRD-17-00662

Despite remarkable efficiency improvements at the cell and module level, thin-film CdTe PV suffers from a significant voltage deficit compared with the ideal. The proposed solution is to build cells with fully depleted absorbers and with energy barriers front and back to direct electrons and holes in appropriate directions. Combined with minimal interfacial recombination, this approach, which is similar to the successful silicon HIT cells, circumvents the need for higher lifetimes and carrier concentration to achieve higher voltage, Colorado State is particularly well-positioned to the address the depleted absorbed architecture. It has robust single-vacuum closed-spaced-sublimation deposition chamber, currently being enhanced with new sources for CdTe alloys and grading. It has made reasonable-efficiency cells with absorbers as thin as 0.3 um, it has demonstrated electron reflection at the rear of the absorber with a continuous CdMgTe layer, it has replaced CdS with MgZnO, which has several advantages including tunable band offsets, and it has achieved 16.8% efficiency. It also has a mature suite of measurement equipment for cell evaluation and the experience to effectively analyze its results for refinement in cell fabrication. Several healthy collaborations will continue within the CdTe community.

14 SOLAR ENERGY↗

DOE OSTI2026

Digital Twin User Guide for Chelan County Public Utility District

This user manual offers a comprehensive guide for developing a Digital twin (DT) of a Kaplan turbine at Chelan County Public Utility District (Chelan PUD) using neural networks. As variable renewable generation expands, hydropower units must operate with optimal efficiency and stability. For Kaplan machines, this flexibility is achieved through coordinated control of guide vane (wicket gates) opening and runner blade pitch, which amplifies the plant’s inherent nonlinear behavior and challenges traditional physics-only modeling. The efficiency of the Kaplan turbine varies with different combinations of the guide vans (wicket gate) opening and the blade angle. Each guide van opening and blade angle has a corresponding highest efficiency point, forming a cam relationship that represents the optimal combination.The discharge of a hydraulic turbine is controlled by the opening angle of the guide vans. Therefore, for each value of head, there is a certain guide van opening and blade angle that corresponds to the highest efficiency. For a given head, different combinations of the guide van opening and blade angle have different efficiencies. Therefore, coordinate cam curves are used to describe the relationship between the wicket gate opening and blade angle with different water head. To address these challenges, the manual details a data-driven modeling and learning workflow centered on structured neural networks. The approach is designed to forecast critical operational variables—discharge flow, net head, penstock (or scroll-case) pressure, and generator electrical outputs—by leveraging real-time inputs such as the generator power control setpoint, exciter field current and field voltage, together with hydromechanical commands (e.g., gate position and, when available, runner blade-pitch angle). The neural models are trained and validated on operational data from a Kaplan unit operated by Chelan PUD, demonstrating that the structured NN architecture can learn the coupled gate–blade–electrical dynamics. The result is a robust DT that improves situational awareness and supports data-informed decision-making for Chelan PUD’s Kaplan turbine operations.

24 POWER TRANSMISSION AND DISTRIBUTION↗

NASA NTRS1971

Nonlinear, nonlaminar-3D computation of electron motion through the output cavity of a klystron

The equations of motion used in the computation are discussed along with the space charge fields and the integration process. The following assumptions were used as a basis for the computation: (1) The beam is divided into N axisymmetric discs of equal charge and each disc into R rings of equal charge. (2) The velocity of each disc, its phase with respect to the gap voltage, and its radius at a specified position in the drift tunnel prior to the interaction gap is known from available large signal one dimensional programs. (3) The fringing rf fields are computed from exact analytical expressions derived from the wave equation assuming a known field shape between the tunnel tips at a radius a. (4) The beam is focused by an axisymmetric magnetic field. Both components of B, that is B sub z and B sub r, are taken into account. (5) Since this integration does not start at the cathode but rather further down the stream prior to entering the output cavity it is assumed that each electron moved along a laminar path from the cathode to the start of integration.

Albers, L. U.↗

NASA NTRS1983

Ultrasonic transducer with a two-dimensional Gaussian field profile

A transducer is described which generates a two-dimensional Gaussian field by controlling both the position of multiple circular electrodes and the voltage applied to each electrode. The transducer is constructed by depositing concentric rings electrodes onto one flat surface of a circular piezoelectric crystal disk and attaching the rings to an impedance matching network which acts as a voltage divider. Geometrical inter-ring separations and electrical inter-ring impedances are designed to minimize the error between the generated acoustic field, modeled as a piecewise linear function, and the desired Gaussian distribution. Total mean squared error between the averaged far-field data and a Gaussian shape is less than two percent.

Claus, R. O.↗

NASA NTRS1999

Low-Pressure Gas Effects on the Potency of an Electron Beam Against Ceramic Cloth

An 8-kv electron beam with a current in the neighborhood of 100 mA from the Ukrainian space welding "Universal Hand Tool" (UHT) burned holes in Nextel AF-62 ceramic cloth designed to withstand temperatures up to 1,427 C. The burnthrough time was on the order of 8 scc at standoff distances between UHT and cloth ranging from 6-24 in. At both closer (2 in.) and farther (48 in.) standoff distances the potency of the beam against the cloth declined and the burnthrough time went up significantly. Prior to the test it had been expected that the beam would lay down a static charge on the cloth and be deflected without damaging the cloth. The burnthrough is thought to be an effect of partial transmission of beam power by a stream of positive ions generated by the high-voltage electron beam from contaminant gas in the "vacuum" chamber. A rough quantitative theoretical computation appears to substantiate this possibility.

Nunes, A. C., Jr.↗

NASA NTRS2006

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Phillips, Thomas A.↗

NASA NTRS2006

NASA Tech Briefs, March 2006

Topics covered include: Medical Signal-Conditioning and Data-Interface System; Instruments for Reading Direct-Marked Data-Matrix Symbols; Processing EOS MLS Level-2 Data; Ground Processing of Data From the Mars Exploration Rovers; Estimating Total Electron Content Using 1,000+ GPS Receivers; NASA Solar Array Demonstrates Commercial Potential; Improved Control of Charging Voltage for Li-Ion Battery; Programmable Pulse-Position-Modulation Encoder; Wavelength-Agile External-Cavity Diode Laser for DWDM; Pattern-Recognition Processor Using Holographic Photopolymer; Submicrosecond Power-Switching Test Circuit; Three-Function Logic Gate Controlled by Analog Voltage; Integrated System for Autonomous Science; Montage Version 3.0; Utilizing AI in Temporal, Spatial, and Resource Scheduling; Satellite Image Mosaic Engine; Architecture for Control of the K9 Rover; HFGMC Enhancement of MAC/GMC; Automated Activation and Deactivation of a System Under Test; Cleaning Carbon Nanotubes by Use of Mild Oxygen Plasmas; Generating Aromatics From CO2 on Mars or Natural Gas on Earth; Attaching Thermocouples by Peening or Crimping; Heat Treatment of Friction-Stir-Welded 7050 Aluminum Plates; Generating Breathable Air Through Dissociation of N2O; High-Performance Scanning Acousto-Ultrasonic System; Correction for Thermal EMFs in Thermocouple Feedthroughs; Using Quasiparticle Poisoning To Detect Photons; Estimating Resolution Lengths of Hybrid Turbulence Models; Education and Training Module in Alertness Management; Cargo-Positioning System for Next-Generation Spacecraft; Micro-Imagers for Spaceborne Cell-Growth Experiments; Holographic Solar Photon Thrusters; Plasma-Based Detector of Outer-Space Dust Particles; and Generation of Data-Rate Profiles of Ka-Band Deep-Space Links.

Source record↗

NASA NTRS1999

Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-(micron)meter MOSFET's with Epitaxial and (delta)-Doped Channels

A detailed three-dimensional (3-D) statistical 'atomistic' simulation study of fluctuation-resistant sub-0.1-(micron)meter MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-(micron)meter generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channel. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-(micron)meter devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta-doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-(micron)meter MOSFET's. Index Terms-Doping, fluctuations, MOSFET, semiconductor device simulation, silicon devices, threshold.

Asenov, Asen↗

NASA NTRS2015

Two-dimensional Inductive Position Sensing System

A two-dimensional inductive position sensing system uses four drive inductors arranged at the vertices of a parallelogram and a sensing inductor positioned within the parallelogram. The sensing inductor is movable within the parallelogram and relative to the drive inductors. A first oscillating current at a first frequency is supplied to a first pair of the drive inductors located at ends of a first diagonal of the parallelogram. A second oscillating current at a second frequency is supplied to a second pair of the drive inductors located at ends of a second diagonal of the parallelogram. As a result, the sensing inductor generates a first output voltage at the first frequency and a second output voltage at the second frequency. A processor determines a position of the sensing inductor relative to the drive inductors using the first output voltage and the second output voltage.

Youngquist, Robert C.↗

NASA NTRS1976

Evaluation of the amperex 56 TVP photomultiplier

Characteristics were measured for the Amperex 56 TVP 42 mm-diameter photomultiplier. Some typical photomultiplier characteristics-such as gain, dark current, transit and rise times-are compared with data provided. Photomultiplier characteristics generally not available such as the single photoelectron time spread, the relative collection efficiency, the relative anode pulse amplitude as a function of the voltage between the photocathode and focusing electrode, and the position of the photocathode sensing area were measured and are discussed for two 56 TVP's. The single photoelectron time spread, the relative collection efficiency, and the transit time difference as a function of the voltage between photocathode and focusing electrode were also measured and are discussed, particularly with respect to the optimization of photomultiplier operating conditions for timing applications.

Lo, C. C.↗

DOE OSTI2023

Balanced current-source inverter

A switching circuit for a current source inverter includes a first inverter leg, a second inverter leg, and a controller. The first inverter leg includes a first reverse-voltage-blocking (RB) switch, a second RB switch, and a third RB switch that are connected in series between a first bus line and a second bus line. The second inverter leg includes a fourth RB switch, a fifth RB switch, and a sixth RB switch are connected in series between the first bus line and the second bus line. The controller is configured to control a switch between an on-state and an off-state for each RB switch. When in the on-state, a reverse voltage is blocked by a respective RB switch, and a current with a positive polarity is conducted through the respective RB switch. When in the off-state, a voltage and the current are blocked by the respective RB switch.

Jahns, Thomas Merlin↗

NASA NTRS2000

Ferroelectric Pump

A ferroelectric pump has one or more variable volume pumping chambers internal to a housing. Each chamber has at least one wall comprising a dome shaped internally prestressed ferroelectric actuator having a curvature and a dome height that varies with an electric voltage applied between an inside and outside surface of the actuator. A pumped medium flows into and out of each pumping chamber in response to displacement of the ferroelectric actuator. The ferroelectric actuator is mounted within each wall and isolates each ferroelectric actuator from the pumped medium, supplies a path for voltage to be applied to each ferroelectric actuator, and provides for positive containment of each ferroelectric actuator while allowing displacement of the entirety of each ferroelectric actuator in response to the applied voltage.

Jalink, Antony, Jr.↗

NASA NTRS1983

Development and fabrication of a high current, fast recovery power diode

A high voltage (VR = 1200 V), high current (IF = 150 A), fast recovery ( 700 ns) and low forward voltage drop ( 1.5 V) silicon rectifier was designed and the process developed for its fabrication. For maximum purity, uniformity and material characteristic stability, neutron transmutation n-type doped float zone silicon is used. The design features a hexagonal chip for maximum area utilization of space available in the DO-8 diode package, PIN diffused junction structure with deep diffused D(+) anode and a shallow high concentration n(+) cathode. With the high temperature glass passivated positive bevel mesa junction termination, the achieved blocking voltage is close to the theoretical limit of the starting material. Gold diffusion is used to control the lifetime and the resulting effect on switching speed and forward voltage tradeoff. For solder reflow assembly, trimetal (Al-Ti-Ni) contacts are used. The required major device electrical characteristics were achieved. Due to the tradeoff nature of forward voltage drop and reverse recovery time, a compromise was reached for these values.

Berman, A. H.↗