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At least 235 records · Page 13

Experimental code verification results for reflector antenna distortion compensation by array feeds

Electronic compensation of reflector surface distortion using array feed with individual amplitude and phase control of the array elements is becoming increasingly attractive because of the recent advances in monolithic microwave integrated circuit (MMIC) technology. An algorithm has been developed previously using the concept of focal plane conjugate field matching in the receive mode and a computer code has been generated that predicts the proper excitation coefficients for the elements of the reflector feed array to compensate the effects of reflector surface distortion. This paper presents the results of an experimental study to verify the above compensation algorithm and in general to demonstrate the effectiveness of the array feed compensation technique.

Zaman, A. J.↗

An Efficient Image Recovery Algorithm for Diffraction Tomography Systems

A diffraction tomography system has potential application in ultrasonic medical imaging area. It is capable of achieving imagery with the ultimate resolution of one quarter the wavelength by collecting ultrasonic backscattering data from a circular array of sensors and reconstructing the object reflectivity using a digital image recovery algorithm performed by a computer. One advantage of such a system is that is allows a relatively lower frequency wave to penetrate more deeply into the object and still achieve imagery with a reasonable resolution. An efficient image recovery algorithm for the diffraction tomography system was originally developed for processing a wide beam spaceborne SAR data...

Jin, Michael Y.↗

An efficient data dependence analysis for parallelizing compilers

A novel algorithm, called the lambda test, is presented for an efficient and accurate data dependence analysis of multidimensional array references. It extends the numerical methods to allow all dimensions of array references to be tested simultaneously. Hence, it combines the efficiency and the accuracy of the both approaches. This algorithm has been implemented in PARAFRASE, a FORTRAN program parallelization restructurer developed at the University of Illinois at Urbana-Champaign. Some experimental results are presented to show its effectiveness.

Li, Zhiyuan↗

Application of Reconfigurable Computing Technology to Multi-KiloHertz Micro-Laser Altimeter (MMLA) Data Processing

The Multi-KiloHertz Micro-Laser Altimeter (MMLA) is an aircraft based instrument developed by NASA Goddard Space Flight Center with several potential spaceflight applications. This presentation describes how reconfigurable computing technology was employed to perform MMLA signal extraction in real-time under realistic operating constraints. The MMLA is a "single-photon-counting" airborne laser altimeter that is used to measure land surface features such as topography and vegetation canopy height. This instrument has to date flown a number of times aboard the NASA P3 aircraft acquiring data at a number of sites in the Mid-Atlantic region. This instrument pulses a relatively low-powered laser at a very high rate (10 kHz) and then measures the time-of-flight of discrete returns from the target surface. The instrument then bins these measurements into a two-dimensional array (vertical height vs. horizontal ground track) and selects the most likely signal path through the array. Return data that does not correspond to the selected signal path are classified as noise returns and are then discarded. The MMLA signal extraction algorithm is very compute intensive in that a score must be computed for every possible path through the two dimensional array in order to select the most likely signal path. Given a typical array size with 50 x 6, up to 33 arrays must be processed per second. And for each of these arrays, roughly 12,000 individual paths must be scored. Furthermore, the number of paths increases exponentially with the horizontal size of the array, and linearly with the vertical size. Yet, increasing the horizontal and vertical sizes of the array offer science advantages such as improved range, resolution, and noise rejection. Due to the volume of return data and the compute intensive signal extraction algorithm, the existing PC-based MMLA data system has been unable to perform signal extraction in real-time unless the array is limited in size to one column, This limits the ability of the MMLA to operate in environments with sparse signal returns and a high number of noise return. However, under an IR&D project, an FPGA-based, reconfigurable computing data system has been developed that has been demonstrated to perform real-time signal extraction under realistic operating constraints. This reconfigurable data system is based on the commercially available Firebird Board from Annapolis Microsystems. This PCI board consists of a Xilinx Virtex 2000E FPGA along with 36 MB of SRAM arranged in five separately addressable banks. This board is housed in a rackmount PC with dual 850MHz Pentium processors running the Windows 2000 operating system. This data system performs all signal extraction in hardware on the Firebird, but also runs the existing "software based" signal extraction in tandem for comparison purposes. Using a relatively small amount of the Virtex XCV2000E resources, the reconfigurable data system has demonstrated to improve performance improvement over the existing software based data system by an order of magnitude. Performance could be further improved by employing parallelism. Ground testing and a preliminary engineering test flight aboard the NASA P3 has been performed, during which the reconfigurable data system has been demonstrated to match the results of the existing data system.

Powell, Wesley↗

Diagonal dominance for the multivariable Nyquist array using function minimization

A new technique for the design of multivariable control systems using the multivariable Nyquist array method was developed. A conjugate direction function minimization algorithm is utilized to achieve a diagonal dominant condition over the extended frequency range of the control system. The minimization is performed on the ratio of the moduli of the off-diagonal terms to the moduli of the diagonal terms of either the inverse or direct open loop transfer function matrix. Several new feedback design concepts were also developed, including: (1) dominance control parameters for each control loop; (2) compensator normalization to evaluate open loop conditions for alternative design configurations; and (3) an interaction index to determine the degree and type of system interaction when all feedback loops are closed simultaneously. This new design capability was implemented on an IBM 360/75 in a batch mode but can be easily adapted to an interactive computer facility. The method was applied to the Pratt and Whitney F100 turbofan engine.

Leininger, G. G.↗

Robotic System Would Inspect Tubes And Fillets

Proposed robotic system inspects arrays of brazed tubes being fabricated for use in heat exchangers and similar objects. Arrays contain coolant tubes mounted in nozzle of main engine of Space Shuttle. Other versions used to inspect components of terrestrial heat exchangers for powerplants, vehicles, and refrigeration equipment. Inspection system provides for automated, complete, objective, and efficient inspection of arrays of coolant tubes. Computer executing image-processing algorithms extracts profiles of tubes and braze fillets and identifies flaws.

Gilbert, Jeffrey L.↗

The wide swath ocean altimeter: radar interferometry for global ocean mapping with centimetric accuracy

We have developed an instrument concept that combines a conventional nadir altimeter with a radar interferometer to meet the above requirements. In this paper, we describe the overall mission concept and the interferometric radar design. We also describe several new technology developments that facilitate the inclusion of this instrument on a small, inexpensive spacecraft bus. Those include ultra-light, deployable reflectarray antennas for the radar interferometer; a novel five frequency feed horn for the radiometer and altimeter; a lightweight, low power integrated three frequency radiometer; and a field programmable gate array-based onboard data processor. Finally, we discuss recent algorithm developments for the onboard date processing, and present the expected instatements performance improvements over previously reported results.

interferometry↗

RFI Risk Reduction Activities Using New Goddard Digital Radiometry Capabilities

The Goddard Radio-Frequency Explorer (GREX) is the latest fast-sampling radiometer digital back-end processor that will be used for radiometry and radio-frequency interference (RFI) surveying at Goddard Space Flight Center. The system is compact and deployable, with a mass of about 40 kilograms. It is intended to be flown on aircraft. GREX is compatible with almost any aircraft, including P-3, twin otter, C-23, C-130, G3, and G5 types. At a minimum, the system can function as a clone of the Soil Moisture Active Passive (SMAP) ground-based development unit [1], or can be a completely independent system that is interfaced to any radiometer, provided that frequency shifting to GREX's intermediate frequency is performed prior to sampling. If the radiometer RF is less than 200MHz, then the band can be sampled and acquired directly by the system. A key feature of GREX is its ability to simultaneously sample two polarization channels simultaneously at up to 400MSPS, 14-bit resolution each. The sampled signals can be recorded continuously to a 23 TB solid-state RAID storage array. Data captures can be analyzed offline using the supercomputing facilities at Goddard Space Flight Center. In addition, various Field Programmable Gate Array (FPGA) - amenable radiometer signal processing and RFI detection algorithms can be implemented directly on the GREX system because it includes a high-capacity Xilinx Virtex-5 FPGA prototyping system that is user customizable.

Bradley, Damon↗

Performance of residual carrier array-feed combining in correlated noise

An array feed combining system for the recovery of signal-to-noise ratio (SNR) loss due to antenna reflector deformation has been implemented and is currently being evaluated on the Jet Propulsion Laboratory's 34-meter DSS-13 antenna. In this system, the defocused signal field captured by a focal plane array feed is recovered using real-time signal-processing and signal-combining techniques. The current signal-processing and signal-combining algorithms are optimum under the assumption that the white Gaussian noise processes in the received signals from different array elements are mutually uncorrelated. Experimental data at DSS 13 indicate that these noise processes are indeed mutually correlated. The main result of this article is an analytical derivation of the actual SNR performance of the current suboptimal signal-combining algorithm in this correlated-noise environment. The analysis here shows that the combined signal SNR can either be improved or degraded depending on the relation between the array signal and noise correlation coefficient phases. Further performance improvement will require the development of signal-combining methods that take into account the correlated noises.

Tan, H. H.↗

Pipeline synthetic aperture radar data compression utilizing systolic binary tree-searched architecture for vector quantization

A system for data compression utilizing systolic array architecture for Vector Quantization (VQ) is disclosed for both full-searched and tree-searched. For a tree-searched VQ, the special case of a Binary Tree-Search VQ (BTSVQ) is disclosed with identical Processing Elements (PE) in the array for both a Raw-Codebook VQ (RCVQ) and a Difference-Codebook VQ (DCVQ) algorithm. A fault tolerant system is disclosed which allows a PE that has developed a fault to be bypassed in the array and replaced by a spare at the end of the array, with codebook memory assignment shifted one PE past the faulty PE of the array.

Chang, Chi-Yung↗

An Analysis of the Lightning Jump Algorithm Using Geostationary Lightning Mapper Flashes

Lightning's relation to severe weather has been studied since the 1980's. The invention of the Lightning Mapping Array allowed for total lightning measurements in a 125 km operational range. This brought forth an automated lightning Jump Algorithm (LIA) that predicted severe weather based on two-sigma increases in total lightning. The LIA's biggest downfall is being restrained to the limited field of view (FOV) of LMA's. The launch of the Geostationary Lightning Mapper (GLM) aboard the GOES-16 satellite now gives us hemispheric total lightning measurements. The wide FOV makes the GLM a good candidate to apply the LIA to. However the GLM and LMA have some differences. One being the coarser spatial resolution of GLM. Another being that LMA measures very high frequency (VHF) electromagnetic radiation while GLM measures optical radiation. These differences suggest an extensive study must be done on using the LIA with GLM to understand potential differences in the LIA and to maximize its operational skill. Four deep dive cases are conducted showcasing the differences between the GLM and LMA and their jumps.

Curtis, Nathan↗

Decoding techniques for fine-fine geometry multi-anode microchannel arrays

The Multi-Anode Microchannel Array (MAMA) is a photon-counting detector which decodes the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. The decoding process can be divided into two tasks: anode encoding and pixel decoding. Techniques for performing both tasks are described and contrasted in light of application requirements. Decode times of 75 nanoseconds have been achieved, and considerably faster decoders are possible given new architectures and technologies.

Kasle, David B.↗

Development of Large-Scale Magnetic Calorimeter Arrays

We describe performance of large-scale arrays of metallic magnetic calorimeters (MMCs) we are developing to meet requirements of the Lynx X-ray Microcalorimeter (LXM) instrument in the astrophysics mission concept Lynx. We have fabricated prototypes with 55,800 x-ray pixels thermally connected to 5,688 MMC sensors. Subarrays demonstrate three types of pixels, which have different energy and spatial resolution goals in LXM. Pixel pitch is 50 or 25 µm. For two subarrays, use of position sensitive detectors, in a "hydra" configuration with 25 x-ray absorbers per sensor, helps achieve a large focal plane by increasing pixel count relative to readout channels. Since each absorber has a different thermal link to its sensor, it generates a different pulse shape and enables discrimination of pixel position. Superconducting wiring from all sensors was brought out to the perimeter of the overall array using multiple buried metal layers planarized by Chemical Mechanical Planarization to achieve high critical current, low inductance, and high fabrication yield. An automated, algorithmic approach was used to layout the complex wiring pattern. For readout with existing small arrays of Superconducting Quantum Interference (SQUID) amplifiers, 112 selected pixels were connected to wire bond pads. In hydras, we successfully identified 25 pulse shapes using rise-time and pulse height. Pulse shapes were similar to simulations. We measured noise and responsivity to substrate temperature and applied x-ray pulses. While we designed sensors to have high inductance to relative to stray inductance of wiring, we had only mismatched (lower input inductance) SQUIDs available in our current apparatus, giving non-optimized resolution. We compared measured and calculated energy resolutions. We have the required sensitivity to reach < 3 eV FWHM resolution for 6 keV x-rays, required for the LXM Main Array, and the ability to discriminate the 25 different absorber pixels down to energies < 300 eV.

microcalorimeters↗

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Stoica, Adrian↗

A Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.

White, Michael J.↗

LU and Cholesky decomposition on an optical systolic array processor

Direct solutions of matrix-vector equations on an optical systolic array processor are considered. The solutions are discussed and a parallel algorithm for LU matrix decomposition that is very attractive for an optical realization is formulated. It is noted that when direct techniques are used, it is preferable to realize the matrix decomposition on an optical system and to utilize a digital processor for the solution of the simplified resultant matrix-vector problem. One method of realizing LU matrix decomposition on a new frequency-multiplexed optical systolic array matrix-matrix processor is described. A simple method for extending the process of LU decomposition to Cholesky decomposition on the optical processor is discussed.

Casasent, D.↗

Leveraging High-Level Synthesis to Migrate Motor Control Algorithms From Microcontroller to FPGA

As motor control algorithms become increasingly complex, traditional microcontroller-based implementations are reaching computational limits that prevent the controller from operating at the required speed. This paper presents a novel workflow leveraging High-Level Synthesis (HLS) to migrate motor control algorithms from a microcontroller implementation to a Field-Programmable Gate Array (FPGA) implementation. The proposed approach utilizes the free Vitis HLS software to automatically convert Embedded Coder-generated C code from a Simulink model into Hardware Description Language (HDL) code suitable for FPGA deployment.

FPGA↗

Leveraging High-Level Synthesis to Migrate Motor Control Algorithms From Microcontroller to FPGA

As motor control algorithms become increasingly complex, traditional microcontroller-based implementations are reaching computational limits that prevent the controller from operating at the required speed. This paper presents a novel workflow leveraging High-Level Synthesis (HLS) to migrate motor control algorithms from a microcontroller implementation to a Field-Programmable Gate Array (FPGA) implementation. The proposed approach utilizes the free Vitis HLS software to automatically convert Embedded Coder-generated C code from a Simulink model into Hardware Description Language (HDL) code suitable for FPGA deployment.

FPGA↗