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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Monitoring Digital Closed-Loop Feedback Systems

A technique of monitoring digital closed-loop feedback systems has been conceived. The basic idea is to obtain information on the performances of closed-loop feedback circuits in such systems to aid in the determination of the functionality and integrity of the circuits and of performance margins. The need for this technique arises as follows: Some modern digital systems include feedback circuits that enable other circuits to perform with precision and are tolerant of changes in environment and the device s parameters. For example, in a precision timing circuit, it is desirable to make the circuit insensitive to variability as a result of the manufacture of circuit components and to the effects of temperature, voltage, radiation, and aging. However, such a design can also result in masking the indications of damaged and/or deteriorating components. The present technique incorporates test circuitry and associated engineering-telemetry circuitry into an embedded system to monitor the closed-loop feedback circuits, using spare gates that are often available in field programmable gate arrays (FPGAs). This technique enables a test engineer to determine the amount of performance margin in the system, detect out of family circuit performance, and determine one or more trend(s) in the performance of the system. In one system to which the technique has been applied, an ultra-stable oscillator is used as a reference for internal adjustment of 12 time-to-digital converters (TDCs). The feedback circuit produces a pulse-width-modulated signal that is fed as a control input into an amplifier, which controls the circuit s operating voltage. If the circuit s gates are determined to be operating too slowly or rapidly when their timing is compared with that of the reference signal, then the pulse width increases or decreases, respectively, thereby commanding the amplifier to increase or reduce, respectively, its output level, and "adjust" the speed of the circuits. The nominal frequency of the TDC s pulse width modulated outputs is approximately 40 kHz. In this system, the technique is implemented by means of a monitoring circuit that includes a 20-MHz sampling circuit and a 24-bit accumulator with a gate time of 10 ms. The monitoring circuit measures the duty cycle of each of the 12 TDCs at a repetition rate of 28 Hz. The accumulator content is reset to all zeroes at the beginning of each measurement period and is then incremented or decremented based of the value of the state of the pulse width modulated signal. Positive or negative values in the accumulator correspond to duty cycles greater or less, respectively, than 50 percent.

Katz, Richard↗
NASA NTRS2007

A CMOS Imager with Focal Plane Compression using Predictive Coding

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Leon-Salas, Walter D.↗
NASA NTRS1985

The development of an interim generalized gate logic software simulator

A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.

Mcgough, J. G.↗
NASA NTRS1973

Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

Source record↗
NASA NTRS1973

The NASA computer aided design and test system

A family of computer programs facilitating the design, layout, evaluation, and testing of digital electronic circuitry is described. CADAT (computer aided design and test system) is intended for use by NASA and its contractors and is aimed predominantly at providing cost effective microelectronic subsystems based on custom designed metal oxide semiconductor (MOS) large scale integrated circuits (LSIC's). CADAT software can be easily adopted by installations with a wide variety of computer hardware configurations. Its structure permits ease of update to more powerful component programs and to newly emerging LSIC technologies. The components of the CADAT system are described stressing the interaction of programs rather than detail of coding or algorithms. The CADAT system provides computer aids to derive and document the design intent, includes powerful automatic layout software, permits detailed geometry checks and performance simulation based on mask data, and furnishes test pattern sequences for hardware testing.

Gould, J. M.↗
NASA NTRS1988

Measuring Critical Charges For Single-Event Upsets

Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.

Buehler, Martin G.↗
NASA NTRS2001

Relative Navigation for Formation Flying of Spacecraft

This paper presents a robust and efficient approach for relative navigation and attitude estimation of spacecraft flying in formation. This approach uses measurements from a new optical sensor that provides a line of sight vector from the master spacecraft to the secondary satellite. The overall system provides a novel, reliable, and autonomous relative navigation and attitude determination system, employing relatively simple electronic circuits with modest digital signal processing requirements and is fully independent of any external systems. Experimental calibration results are presented, which are used to achieve accurate line of sight measurements. State estimation for formation flying is achieved through an optimal observer design. Also, because the rotational and translational motions are coupled through the observation vectors, three approaches are suggested to separate both signals just for stability analysis. Simulation and experimental results indicate that the combined sensor/estimator approach provides accurate relative position and attitude estimates.

Alonso, Roberto↗
NASA NTRS1981

Development of design, qualification, screening, and application requirements for plastic encapsulated solid-state devices for space applications

Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.

Source record↗
NASA NTRS1972

Light-detection electronics for a Raman lidar

A light-detection system for an optical radar, or lidar, unit to be used for remote temperature and composition measurements was designed, built, and bench tested. This detection system processes three return signal wavelengths: two Raman wavelengths, and the Rayleigh-Mie wavelength at 694.3 nanometers. Means of coping with photomultiplier tube instabilities and limitations are discussed. Circuits for gain control, ranging, and digitizing are included. The phototube gains can be switched fully on in 80 meters (450 nsec) or off in 30 meters (200 nsec) of range. The range circuit processes signals from 0.1 to 2 kilometers, with an estimated range resolution of less than 5 meters.

Leser, R. J.↗
NASA NTRS1986

DSP-based non-coherent dual detector demodulator for land mobile radio channels

This paper outlines the development of a digital demodulator suitable for the non-coherent detection of various modulation formats including: Phase Shift Keying (PSK), Continuous Phase Frequency Shift Keying (CPFSK) and Frequency Modulation (FM). The demodulator design concept has been derived with a view towards a single integrated circuit (IC) implementation. Two detectors, one non-coherent and one differentially coherent, operate concurrently, providing data detection and automatic frequency control (AFC). Bit error rate results are provided which illustrate the receiver performance in white Gaussian noise.

Saulnier, Gary J.↗
NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗
NASA NTRS1993

Total Ionizing Dose Effects in 12-Bit Successive-Approximation Analog-To-Digital Converters

Analog-to-digital (A/D) converters are critical components in many space and military systems, and there have been numerous advances in A/D converter technology that have increased the resolution and conversion time. The increased performance is due to two factors: (1) advances in circuit design and complexity, which have increased the number of components and the integration density; and (2) new process technologies, such as BiCMOS, which provide better performance, cost, and smaller size in mixed-signal circuits. High-speed A/D converters, with conversion rates above 1 MHz, present a challenge to circuit designers and test engineers. Their complex architectures and high-performance specifications result in numerous possible failure modes when they are subjected to ionizing radiation. The dominant failure mode may depend on the specific application because the fundamental effects on MOS and bipolar transistors are strongly affected by bias conditions.

Lee, C. I.↗
NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗
NASA NTRS1977

A digital goniometer for VOR

A new VOR (VHF omni-range) goniometer design which promises to improve the reliability and maintainability of the VOR ground station is described. The heart of the new concept is the use of two digital phase shifters to produce the rotating figure-of-eight pattern of conventional VOR. Using digital circuits, the goniometer adjustments and calibration reduce to timing adjustments of binary signals. A common clock used for timing the digital phase shifters also synchronizes the 30 Hz modulation of the 9.96 kHz reference.

Meer, S. A.↗
NASA NTRS1980

Payload/orbiter signal processing and data handling system evaluation presentation

It is recommended that standard digital and along interfaces be adopted. These include: (1) define interfaces compatible with NASA/DOD/industry-accepted design standards; (2) investigate costs of modifying orbiter sybsystem interfaces, (3) investigate cost of designing attached payload interface unit for NASA and commercial payloads and (4) investigate costs of designing interface circuits that can be incorporated into each payload design.

Source record↗
NASA NTRS1997

Ultra Small Aperture Terminal for Ka-Band SATCOM

An ultra small aperture terminal (USAT) at Ka-band frequency has been developed by Lewis Research Center (LeRC) for data rates up to 1.5 Mbps in the transmit mode and 40 Mbps in receive mode. The terminal consists of a 35 cm diameter offset-fed parabolic antenna which is attached to a solid state power amplifier and low noise amplifier. A single down converter is used to convert the Ka-band frequency to 70 MHz intermediate frequency (IF). A variable rate (9.6 Kbps to 10 Mbps) commercial modem with a standard RS-449/RS-232 interface is used to provide point-to-point digital services. The terminal has been demonstrated numerous times using the Advanced Communications Technology Satellite (ACTS) and the 4.5 in Link Evaluation Terminal (LET) in Cleveland. A conceptual design for an advanced terminal has also been developed. This advanced USAT utilizes Microwave Monolithic Integrated Circuit (MMIC) and flat plate array technologies. This terminal will be self contained in a single package which will include a 1 watt solid state amplifier (SSPA), low noise amplifier (LNA) and a modem card located behind the aperture of the array. The advanced USAT will be light weight, transportable, low cost and easy to point to the satellite. This paper will introduce designs for the reflector based and array based USAT's.

Acosta, Roberto↗
NASA NTRS2014

All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Shuler, Robert L., Jr.↗
NASA NTRS2014

ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Schuler, Robert L., Jr.↗