Design of fault-tolerant computers.
Logic fault tolerant digital computer design for increased reliability, discussing logic circuits and protective redundancy
Avizienis, A.↗
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High frequency capacitor-diode voltage multiplier dc-dc converter development
A power conditioner was developed which used a capacitor diode voltage multiplier to provide a high voltage without the use of a step-up transformer. The power conditioner delivered 1200 Vdc at 100 watts and was operated from a 120 Vdc line. The efficiency was in excess of 90 percent. The component weight was 197 grams. A modified boost-add circuit was used for the regulation. A short circuit protection circuit was used which turns off the drive circuit upon a fault condition, and recovers within 5 ms after removal of the short. High energy density polysulfone capacitors and high speed diodes were used in the multiplier circuit.
Kisch, J. J.↗
Design and Development of the Solar Dynamics Observatory (SDO) Electrical Power System
The SDO spacecraft was designed to help us understand the Sun's influence on Earth and Near-Earth space by studying the solar atmosphere on small scales of space and time and in many wavelengths simultaneously. It will perform its operations in a geosynchronous orbit of the earth. This paper will present background on the SDO mission, an overview of the design and development activities associated specifically with the SDO electrical power system (EPS), as well as the major driving requirements behind the mission design. The primary coverage of the paper will be devoted to some of the challenges faced during the design and development phase. This will include the challenges associated with development of a compatible CompactPCI (cPCI) interface within the Power System Electronics (PSE) in order to utilize a "common" processor card, implementation of new solid state power controllers (SSPC) for primary load distribution switching and over current protection in the PSE, and the design approach adopted to meet single fault tolerance requirements for all of the SDO EPS functions.
Denney, Keys↗
Power processor for a 20CM ion thruster
A power processor breadboard for the JPL 20CM Ion Engine was designed, fabricated, and tested to determine compliance with the electrical specification. The power processor breadboard used the silicon-controlled rectifier (SCR) series resonant inverter as the basic power stage to process all the power to the ion engine. The breadboard power processor was integrated with the JPL 20CM ion engine and complete testing was performed. The integration tests were performed without any silicon-controlled rectifier failure. This demonstrated the ruggedness of the series resonant inverter in protecting the switching elements during arcing in the ion engine. A method of fault clearing the ion engine and returning back to normal operation without elaborate sequencing and timing control logic was evolved. In this method, the main vaporizer was turned off and the discharge current limit was reduced when an overload existed on the screen/accelerator supply. After the high voltage returned to normal, both the main vaporizer and the discharge were returned to normal.
Biess, J. J.↗
Mars geologic mapping program: Review and highlights
The Mars Geologic Mapping (MGM) Program was introduced by NASA in 1987 as a new initiative in the Planetary Geology and Geophysics (PGG) Program. The overall purpose of the program is to support research on topical science problems that address specific questions. Among the objectives of the project are: (1) to produce highly detailed geologic maps that will greatly increase the knowledge of the materials and processes that have contributed to the evolutionary history of Mars; (2) to define areas of special interest for possible future investigation by planned missions (Mars Observer, Mars Sample Return); and (3) to maintain the interest of the planetary community in the development of new concepts and the re-evaluation of Martian geology as new data in usable form become available. Some interesting highlights of the geologic mapping indicate that multiple flood episodes occurred at different times during the Hesperian Period in both Kasei and Maja Valles. Studies of small channels in the Memnonia, Mangala, and Tharsis regions show that fluvial events appear to have occurred during the Amazonian Period at equatorial latitudes. Flood waters occurred during the Amazonian Period at equatorial latitudes. Flood waters from Mangala Valles may have seeped into surficial materials with the subsequent development of numerous sapping channels and debris flows; this suggests that the ancient highland terrain consists of relatively unconsolidated materials. Multiple layers were observed for the first time in the ridged plains lava flows covering large areas of Lunae Planum; some wrinkle ridges in this area are associated with grabens and collapse volcanic units at Hadriaca and Tyrrhena Paterae indicates that the units may have been emplaced by gravity-driven pyroclastic flows. Unlike the north polar layered deposits, those in the south polar region show no angular unconformities or evidence of faulting and folding. Water ice in the south polar layered deposits may be protected from solar heating and sublimation by a weathering rind or lag deposit on the surface.
Scott, David H.↗
Watchdog activity monitor (WAM) for use wth high coverage processor self-test
A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor's clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.
Tulpule, Bhalchandra R.↗
Use of Field Programmable Gate Array Technology in Future Space Avionics
Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.
Ferguson, Roscoe C.↗
NASA Tech Briefs, August 2004
Topics covered include: Data Relay Board with Protocol for High-Speed, Free-Space Optical Communications; Software and Algorithms for Biomedical Image Data Processing and Visualization; Rapid Chemometric Filtering of Spectral Data; Prioritizing Scientific Data for Transmission; Determining Sizes of Particles in a Flow from DPIV Data; Faster Processing for Inverting GPS Occultation Data; FPGA-Based, Self-Checking, Fault-Tolerant Computers; Ultralow-Power Digital Correlator for Microwave Polarimetry; Grounding Headphones for Protection Against ESD; Lightweight Stacks of Direct Methanol Fuel Cells; Highly Efficient Vector-Inversion Pulse Generators; Estimating Basic Preliminary Design Performances of Aerospace Vehicles; Framework for Development of Object-Oriented Software; Analyzing Spacecraft Telecommunication Systems; Collaborative Planning of Robotic Exploration; Tools for Administration of a UNIX-Based Network; Preparing and Analyzing Iced Airfoils; Evaluating Performance of Components; Fuels Containing Methane of Natural Gas in Solution; Direct Electrolytic Deposition of Mats of MnxOy Nanowires; Bubble Eliminator Based on Centrifugal Flow; Inflatable Emergency Atmospheric-Entry Vehicles; Lightweight Deployable Mirrors with Tensegrity Supports; Centrifugal Adsorption Cartridge System; Ultrasonic Apparatus for Pulverizing Brittle Material; Transplanting Retinal Cells using Bucky Paper for Support; Using an Ultrasonic Instrument to Size Extravascular Bubbles; Coronagraphic Notch Filter for Raman Spectroscopy; On-the-Fly Mapping for Calibrating Directional Antennas; Working Fluids for Increasing Capacities of Heat Pipes; Computationally-Efficient Minimum-Time Aircraft Routes in the Presence of Winds; Liquid-Metal-Fed Pulsed Plasma Thrusters; Personal Radiation Protection System; and Attitude Control for a Solar-Sail Spacecraft.
Source record↗
Modeling Spacecraft Safe Mode Events
Spacecraft enter a ‘safe mode’ to protect the vehicle when a potentially harmful anomaly occurs. This minimally functioning state isolates faults, establishes contact with Earth, and orients the vehicle into a power positive attitude until operators intervene. Though ‘safings’ are inherently unpredictable, mission teams build in time margin during operations to determine root causes and restore functionality. Planning and managing this margin is both critical and enabling on mission architectures dependent on near-continuous operability – such as a low-thrust electric propulsion mission. To better quantify the occurrences and severity of safe mode anomalies, the Jet Propulsion Laboratory (JPL) has assembled a database of safings from past and active missions. Currently nearly 240 records are captured from 21 beyond-Earth missions, stemming from a collaboration between teams at JPL, Ames Research Center, Goddard Space Flight Center, and the Johns Hopkins University Applied Physics Laboratory. This paper discusses the event database, explores a statistical approach in modeling the occurrences and severity of safing events, presents a simulation technique, and details recommendations and future work to benefit future concepts.
Nicholas, Austin↗
Circuit protects regulated power supply against overload current
Sensing circuit in which a tunnel diode controls a series regulator transistor protects a low voltage transistorized dc regulator from damage by excessive load currents. When a fault occurs, the faulty circuit is limited to a preset percentage of the current when limiting first occurs.
Airth, H. B.↗
Kilovolt dc solid state remote power controller development
The experience gained in developing and applying solid state power controller (SSPC) technology at high voltage dc (HVDC) potentials and power levels of up to 25 kilowatts is summarized. The HVDC switching devices, power switching concepts, drive circuits, and very fast acting overcurrent protection circuits were analyzed. A 25A bipolar breadboard with Darlington connected switching transistor was built. Fault testing at 900 volts was included. A bipolar transistor packaged breadboard design was developed. Power MOSFET remote power controller (RPC) was designed.
Mitchell, J. T.↗
Fault Management Metrics
This paper describes the theory and considerations in the application of metrics to measure the effectiveness of fault management. Fault management refers here to the operational aspect of system health management, and as such is considered as a meta-control loop that operates to preserve or maximize the system's ability to achieve its goals in the face of current or prospective failure. As a suite of control loops, the metrics to estimate and measure the effectiveness of fault management are similar to those of classical control loops in being divided into two major classes: state estimation, and state control. State estimation metrics can be classified into lower-level subdivisions for detection coverage, detection effectiveness, fault isolation and fault identification (diagnostics), and failure prognosis. State control metrics can be classified into response determination effectiveness and response effectiveness. These metrics are applied to each and every fault management control loop in the system, for each failure to which they apply, and probabilistically summed to determine the effectiveness of these fault management control loops to preserve the relevant system goals that they are intended to protect.
Johnson, Stephen B.↗
Modifying real convolutional codes for protecting digital filtering systems
A novel method is proposed for protecting digital filters from temporary and permanent failures that are not easily detected by conventional fault-tolerant computer design principles, on the basis of the error-detecting properties of real convolutional codes. Erroneous behavior is detected by externally comparing the calculated and regenerated parity samples. Great simplifications are obtainable by modifying the code structure to yield simplified parity channels with finite impulse response structures. A matrix equation involving the original parity values of the code and the polynomial of the digital filter's transfer function is formed, and row manipulations separate this equation into a set of homogeneous equations constraining the modifying scaling coefficients and another set which defines the code parity values' implementation.
Redinbo, G. R.↗
Aerospace technology development of three types of solid state remote power controllers for 120VDC with current ratings of five, and thirty amperes, one type having current limiting
The first generation of remote power controllers (RPC) developed included: a 5-ampere design (Type 1), capable of limiting maximum overload current to 15 amperes for .1 sec; and 5-ampere noncurrent (Type 2) and 30-ampere noncurrent (Type 3) limiting designs, both with selectable instant trip levels for high-current overload. Each design provides overcurrent protection through an inverse I squared T trip-out function with an automatic reset option and demonstrates step-applied fault capability with a 4000-ampere surge, fast-risetime (low-inductance) power source. They also meet MIL - STD - 461A specification for electromagnetic interference. The second generation RPCs traded off specification compliance for reduction in cost and complexity for the Type 1 and 2 designs and give comparable or improved performance in most areas. The noncurrent limiting RPC proved to be a more economical and feasible method of overload protection for certain load types.
Baker, D. E.↗
Toward achieving global sole means radionavigation systems
This paper briefly reviews tentative requirements for global, earth-referenced sole means of navigation systems with emphasis on integrity and availability. These requirements can be allocated to integrated navigation system architectures based on for instance GPS, GLONASS, VOR/DME, TACAN, Omega, Chayka, and Loran-C. Fault detection and isolation techniques (FDI) for integrated radio navigation systems are presented. The FDI algorithm provides a protection radius with a specified confidence level as a function of measurement geometry and algorithm requirements. This is followed by a case study of integrated GPS/Loran-C.
Vangraas, F.↗
Fault Management Guiding Principles
Regardless of the mission type: deep space or low Earth orbit, robotic or human spaceflight, Fault Management (FM) is a critical aspect of NASA space missions. As the complexity of space missions grows, the complexity of supporting FM systems increase in turn. Data on recent NASA missions show that development of FM capabilities is a common driver for significant cost overruns late in the project development cycle. Efforts to understand the drivers behind these cost overruns, spearheaded by NASA's Science Mission Directorate (SMD), indicate that they are primarily caused by the growing complexity of FM systems and the lack of maturity of FM as an engineering discipline. NASA can and does develop FM systems that effectively protect mission functionality and assets. The cost growth results from a lack of FM planning and emphasis by project management, as well the maturity of FM as an engineering discipline, which lags behind the maturity of other engineering disciplines. As a step towards controlling the cost growth associated with FM development, SMD has commissioned a multi-institution team to develop a practitioner's handbook representing best practices for the end-to-end processes involved in engineering FM systems. While currently concentrating primarily on FM for science missions, the expectation is that this handbook will grow into a NASA-wide handbook, serving as a companion to the NASA Systems Engineering Handbook. This paper presents a snapshot of the principles that have been identified to guide FM development from cradle to grave. The principles range from considerations for integrating FM into the project and SE organizational structure, the relationship between FM designs and mission risk, and the use of the various tools of FM (e.g., redundancy) to meet the FM goal of protecting mission functionality and assets.
principles↗
Voyager at Uranus
The engineering changes that had to be made in the Voyager 2 spacecraft in order to enable it to fly beyond the originally planned encounters with Jupiter and Saturn and the underlying engineering strategy leading to the encounter with Uranus are discussed. Fixes of the azimuth actuator failure, receiver failure, and memory failure, and capability upgrades of Image Data Compression, aperture augmentation protective coding, smear reduction, Image Motion Compensation, power management, and contingency planning are summarized. The use of the Computer Command Subsystem in the extension of the voyage is described. The ways in which the strategic priorities, including spacecraft preservation, protection of the near-encounter load, development of new ground and spacecraft capabilities, and repair or circumvention of existing spacecraft faults, were accomplished are reviewed, and the accomplishment of additional tasks is also discussed.
Mclaughlin, W. I.↗
Redundant Buses For Loosely Coupled Dual Computers
Digital electronic network contains two data processors loosely coupled to each other and to four remote terminals via three MIL-STD-1553B data buses. Three-bus configuration provides redundancy for protection against failure of one of the processors and against failures of one or two buses. Triple-bus architecture used for fault tolerance in similar terrestrial digital electronic systems.
Katz, Richard B.↗