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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13

System design and installation for RS600 programmable control system for solar heating and cooling

Procedures for installing, operating, and maintaining a programmable control system which utilizes a F8 microprocessor to perform all timing, control, and calculation functions in order to customize system performance to meet individual requirements for solar heating, combined heating and cooling, and/or hot water systems are described. The manual discusses user configuration and options, displays, theory of operation, trouble-shooting procedures, and warranty and assistance. Wiring lists, parts lists, drawings, and diagrams are included.

Source record↗

A design approach to real-time formatting of high speed multispectral image data

A design approach to formatting multispectral image data in real time at very high data rates is presented for future onboard processing applications. The approach employs a microprocessor-based alternating buffer memory configuration whose formatting function is completely programmable. Data are read from an output buffer in the desired format by applying the proper sequence of addresses to the buffer via a lookup table memory. Sensor data can be processed using this approach at rates limited by the buffer memory access time and the buffer switching process delay time. This design offers flexible high speed data processing and benefits from continuing increases in the performance of digital memories.

Meredith, B. D.↗

Analytical theory for artificial satellites

A theory for generating segmented ephemerides is discussed as a means for fast generation and simple retrieval of nominal orbit data. Over a succession of finite intervals of time, the orbit is represented by a best approximation expressed by Chebyshev polynomials. Storage of coefficients tables for Chebyshev polynomials is seen as a method to reduce data and decrease transmission costs. A general algorithm was constructed and computer programs were designed. The possibility of storing an ephemeris for a few days in the on-board computer, or in microprocessors attached to the data collectors is suggested.

Deprit, A.↗

The performance of NASA research hydrogen masers

Field operable hydrogen masers based on prior maser designs are presented. These units incorporate improvements in magnetic shielding, lower noise electronics, better thermal control, and have a microprocessor for operation, monitoring, and diagnostic functions. They are ruggedly built for transportability and ease of service anywhere in the world.

Reinhardt, V. S.↗

CCD sensors for interplanetary spacecraft navigation and pointing control

The applications of practical optical image sensing CCDs to interplanetary spacecraft precision science payload delivery are discussed. The increasing demand for precision and flexibility in spacecraft for proposed new missions is forcing a transition to autonomous onboard navigation and pointing control. Onboard processing of video data is a crucial element in this transition and is made possible by CCD imagers and microprocessors. The pending Halley's comet close flyby is used as an example to examine details of the sensor design and the data processing which will meet the requirements. Target body centerfinding for optical navigation, target body tracking signal processing, and CCD sensor heads are examined, and flow charts and block diagrams are given for each.

Eisenman, A. R.↗

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗

Electromechanical actuation for thrust vector control applications

At present, actuation systems for the Thrust Vector Control (TVC) for launch vehicles are hydraulic systems. The Advanced Launch System (ALS), a joint initiative between NASA and the Air Force, is a launch vehicle that is designed to be cost effective, highly reliable and operationally efficient with a goal of reducing the cost per pound to orbit. As part of this initiative, an electromechanical actuation system is being developed as an attractive alternative to the hydraulic systems used today. NASA-Lewis is developing and demonstrating an Induction Motor Controller Actuation System with a 40 hp peak rating. The controller will integrate 20 kHz resonant link Power Management and Distribution (PMAD) technology and Pulse Population Modulation (PPM) techniques to implement Field Oriented Vector Control (FOVC) of a new advanced induction motor. Through PPM, multiphase variable frequency, variable voltage waveforms can be synthesized from the 20 kHz source. FOVC shows that varying both the voltage and frequency and their ratio (V/F), permits independent control of both torque and speed while operating at maximum efficiency at any point on the torque-speed curve. The driver and the FOVC will be microprocessor controlled. For increased system reliability, a Built-in Test (BITE) capability will be included. This involves introducing testability into the design of a system such that testing is calibrated and exercised during the design, manufacturing, maintenance and prelaunch activities. An actuator will be integrated with the motor controller for performance testing of the EMA TVC system. The design and fabrication of the motor controller is being done by General Dynamics Space Systems Division. The University of Wisconsin-Madison will assist in the design of the advanced induction motor and in the implementation of the FOVC theory. A 75 hp electronically controlled dynamometer will be used to test the motor controller in all four quadrants of operation using flight type control algorithms. Integrated testing of the controller and actuator will be conducted at a facility yet to be named. The EMA system described above is discussed in detail.

Roth, Mary Ellen↗

Application of microprocessors to spacecraft synthetic aperture radar processing

A ground-based digital synthetic aperture radar (SAR) processor capable of correlating images from raw spacecraft data at real-time rates is currently under development. The processor design requirements are particularly formidable due to (1) range migration effects resulting from planetary curvature and rotation, (2) antenna beam pointing errors, and (3) variation of the Doppler reference function with changing orbital parameters. Based upon the current effort, this paper describes a candidate real-time on-board SAR processing implementation approach that might evolve for future spacecraft applications. Key features include the use of custom large scale integration (LSI) charge-coupled device (CCD) technology to accomplish the correlation functions and microprocessor technology to effect control.

Arens, W. E.↗

Towards the formal specification of the requirements and design of a processor interface unit

Work to formally specify the requirements and design of a Processor Interface Unit (PIU), a single-chip subsystem providing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system, is described. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance free operation, or both. The approaches that were developed for modeling the PIU requirements and for composition of the PIU subcomponents at high levels of abstraction are described. These approaches were used to specify and verify a nontrivial subset of the PIU behavior. The PIU specification in Higher Order Logic (HOL) is documented in a companion NASA contractor report entitled 'Towards the Formal Specification of the Requirements and Design of a Processor Interfacs Unit - HOL Listings.' The subsequent verification approach and HOL listings are documented in NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit' and NASA contractor report entitled 'Towards the Formal Verification of the Requirements and Design of a Processor Interface Unit - HOL Listings.'

Fura, David A.↗

CHOMPTT (CubeSat Handling of Multisystem Precision Timing Transfer): From Concept to Launch Pad

Here we present the evolution of a student satellite mission: CHOMPTT (CubeSat Handling of Multisystem Precision Time Transfer), from its original concept as a candidate for the University NanoSatellite Program 8 (UNP8), to a spacecraft ready for launch in Fall of 2017 on ELaNa XIX (Educational Launch of Nanosatellites). The 3U CubeSat houses a 1 kg, 1U OPTI (Optical Precision Timing Instrument) payload, designed and built at the University of Florida, and a 1.5U EDSNNODeS-derived bus from NASA Ames Research Center. The OPTI payload comprises of: 1) a supervisor board that handles payload data, power regulation, and mode settings, 2) an optics assembly of six 1 cm retroreflectors and four laser beacon diodes for ground-tracking; and 3) two fully redundant timing channels, each consisting of: a chip-scale atomic clock, a microprocessor with clock counter, a picosecond event timer, and an avalanche photodetector (APD) with band-pass filter. Several iterations of OPTI have been developed, tested, and designed to achieve its current functionality and design a laboratory breadboard design, a 1.5U high altitude balloon design, engineering unit design, and its current flight unit design. In-lab testing of the current OPTI design indicates a short-term precision of 100 ps, equivalent to a range accuracy of 3 cm necessary to achieve our primary objective of 200 ps time transfer error, and a long-term timing accuracy of 20 ns over one orbit (1.5 hours). After the spacecraft reaches its nominal 500 km orbit at a 85 degree inclination, an experimental laser ranging facility at Kennedy Space Center in Florida, will track and emit 1064 nm nanosecond optical pulses at the CHOMPTT spacecraft. The laser pulses will then reflect off the retroreflector array mounted on the nadir face of CHOMPTT, and return the pulse to the laser ranging facility where the laser ranging facility will record the round-trip duration of the laser pulses. At the same time the pulse arrives at the spacecraft and is reflected by the array, an APD will record the arrival time of the pulses at the nanosatellite. By comparing the arrival of the pulse at the CubeSat and the duration of the round-trip of the laser pulse, the clock discrepancy between the ground and CubeSat atomic clocks can be determined, in addition to the CubeSats range from the facility. The design and verification of the flight version of CHOMPTT will be reviewed and an overview of the lifetime development and progression of CHOMPTT from the inception to launch pad will be presented.

CHOMPTT↗

FPGA Coprocessor Design for an Onboard Multi-Angle Spectro-Polarimetric Imager

A multi-angle spectro-polarimetric imager (MSPI) is an advanced camera system currently under development at JPL for possible future consideration on a satellite-based Aerosol-Cloud-Environ - ment (ACE) interaction study. The light in the optical system is subjected to a complex modulation designed to make the overall system robust against many instrumental artifacts that have plagued such measurements in the past. This scheme involves two photoelastic modulators that are beating in a carefully selected pattern against each other. In order to properly sample this modulation pattern, each of the proposed nine cameras in the system needs to read out its imager array about 1,000 times per second. The onboard processing required to compress this data involves least-squares fits (LSFs) of Bessel functions to data from every pixel in realtime, thus requiring an onboard computing system with advanced data processing capabilities in excess of those commonly available for space flight. As a potential solution to meet the MSPI onboard processing requirements, an LSF algorithm was developed on the Xilinx Virtex-4FX60 field programmable gate array (FPGA). In addition to configurable hardware capability, this FPGA includes Power -PC405 microprocessors, which together enable a combination hardware/ software processing system. A laboratory demonstration was carried out based on a hardware/ software co-designed processing architecture that includes hardware-based data collection and least-squares fitting (computationally), and softwarebased transcendental function computation (algorithmically complex) on the FPGA. Initial results showed that these calculations can be handled using a combination of the Virtex- 4TM Power-PC core and the hardware fabric.

Pingree, Paula J.↗

The digital control of an experiment to size particles using a laser

Efforts to automate an experiment for sizing particles using a laser is described. The objective of the experiment was to rotate a photomultiplier detector at various angles and to record data associated with how light interacted with a particle. The light source was a laser which was fixed in space. The design consisted of a step motor with a fabricated electromechanical system to rotate the photomultiplier. The use of an 8080 microprocessor based microcomputer to control the step motor and to log data is described.

Cross, J. E.↗

An integrated exhaust gas analysis system with self-contained data processing and automatic calibration

An integrated gas analysis system designed to operate in automatic, semiautomatic, and manual modes from a remote control panel is described. The system measures the carbon monoxide, oxygen, water vapor, total hydrocarbons, carbon dioxide, and oxides of nitrogen. A pull through design provides increased reliability and eliminates the need for manual flow rate adjustment and pressure correction. The system contains two microprocessors to range the analyzers, calibrate the system, process the raw data to units of concentration, and provides information to the facility research computer and to the operator through terminal and the control panels. After initial setup, the system operates for several hours without significant operator attention.

Anderson, R. C.↗

Development of a simple, self-contained flight test data acquisition system

The flight test system described combines state-of-the-art microprocessor technology and high accuracy instrumentation with parameter identification technology which minimize data and flight time requirements. The system was designed to avoid permanent modifications of the test airplane and allow quick installation. It is capable of longitudinal and lateral-directional stability and control derivative estimation. Details of this system, calibration and flight test procedures, and the results of the Cessna 172 flight test program are presented. The system proved easy to install, simple to operate, and capable of accurate estimation of stability and control parameters in the Cessna 172 flight tests.

Clarke, R.↗

PPOD Programmable pilot-oriented display

A general-purpose low cost research microprocessor system for general aviation was developed. This system is intended to be the vehicle for individual research efforts in low cost airborne hardware and software as well as advanced microprocessor based navigation systems and techniques. Two such research projects were undertaken, yielding results in the areas of micro hardware/software design, cost and performance, and pilot/computer interface. Low-cost flight software reliability and a time-difference based Loran approach procedure that eliminates the need for propagation corrections and latitude/longitude transformations are also discussed.

Elias, A. L.↗

A simple, low cost application of a flight test parameter identification system

The flight test system combines state-of-the-art microprocessor technology and high accuracy instrumentation with parameter identification technology which minimize data and flight time requirements. The system was designed to avoid permanent modifications of the test airplane and allow quick installation. It is capable of longitudinal and lateral-directional stability and control derivative estimation. This paper presents details of this system, calibration and flight test procedures, and the results of the Cessna 172 flight test program. The system has proven easy to install, simple to operate, and capable of accurate estimation of stability and control parameters in the Cessna 172 flight tests.

Clarke, R.↗