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Results for “reconfigurable hardware”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS1989

Merlin - Massively parallel heterogeneous computing

Hardware and software for Merlin, a new kind of massively parallel computing system, are described. Eight computers are linked as a 300-MIPS prototype to develop system software for a larger Merlin network with 16 to 64 nodes, totaling 600 to 3000 MIPS. These working prototypes help refine a mapped reflective memory technique that offers a new, very general way of linking many types of computer to form supercomputers. Processors share data selectively and rapidly on a word-by-word basis. Fast firmware virtual circuits are reconfigured to match topological needs of individual application programs. Merlin's low-latency memory-sharing interfaces solve many problems in the design of high-performance computing systems. The Merlin prototypes are intended to run parallel programs for scientific applications and to determine hardware and software needs for a future Teraflops Merlin network.

Wittie, Larry↗
NASA NTRS1975

Impact of coverage on the reliability of a fault tolerant computer

A mathematical reliability model is established for a reconfigurable fault tolerant avionic computer system utilizing state-of-the-art computers. System reliability is studied in light of the coverage probabilities associated with the first and second independent hardware failures. Coverage models are presented as a function of detection, isolation, and recovery probabilities. Upper and lower bonds are established for the coverage probabilities and the method for computing values for the coverage probabilities is investigated. Further, an architectural variation is proposed which is shown to enhance coverage.

Bavuso, S. J.↗
NASA NTRS1982

Design and evaluation of a fault-tolerant multiprocessor using hardware recovery blocks

A fault-tolerant multiprocessor with a rollback recovery mechanism is discussed. The rollback mechanism is based on the hardware recovery block which is a hardware equivalent to the software recovery block. The hardware recovery block is constructed by consecutive state-save operations and several state-save units in every processor and memory module. When a fault is detected, the multiprocessor reconfigures itself to replace the faulty component and then the process originally assigned to the faulty component retreats to one of the previously saved states in order to resume fault-free execution. A mathematical model is proposed to calculate both the coverage of multi-step rollback recovery and the risk of restart. A performance evaluation in terms of task execution time is also presented.

Lee, Y. H.↗
NASA NTRS2005

Evolvable hardware system at extreme low temperatures

This paper describes circuit evolutionary experiments at extreme low temperatures, including the test of all system components at this extreme environment (EE). In addition to hardening-by-process and hardening-by-design, 'hardening-by-reconfiguration ', when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive selfreconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. This paper demonstrates this technique for circuit evolution and recovery at liquid nitrogen temperatures (-196.6 (deg)C). In addition, preliminary tests are performed to assess the survivability limitations of the evolutionary processor at extreme low temperatures.

evolvable harware↗
NASA NTRS1990

A robotic return to the moon

The autonomous lunar precursor mission presently proposed for low cost manned revisits to the lunar surface, designated 'Lunar Oasis by Automation and Robotics', employs two self-similar robotic vehicles, and three experimental 'biovolumes' which are directly derived from the lunar landers that are initially entrusted with fulfilling mission hardware-delivery requirements. The two vehicles would support the experimental biovolumes by returning resources for use in physicochemical or biological processing. Delivered resources would be combined with those in situ to furnish reconfigured biovolumes with the capabilities for autonomous biological growth and wastes-reprocessing demonstrations.

Luttges, Marvin W.↗
NASA NTRS2014

Dynamically Reconfigurable Systolic Array Accelorators

A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Dasu, Aravind↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Gwaltney, David A.↗
NASA NTRS1989

A scheme for fault tolerance in earth sensors

A system is presented that uses dual-redundant earth sensors to measure pitch and roll errors of a three-axis stabilized spacecraft, with provision for (1) autonomously detecting and identifying a faulty earth sensor, and (2) automatically selecting the outputs of the fault-free sensor for closed-loop attitude control, before failures cause major problems. A brief description is given of the system, and various failure modes of earth sensors and their effects are discussed. Novel techniques and algorithms for automatic fault detection, identification, and reconfiguration (FDIR) of dual-redundant earth sensors are developed. The algorithms are validated through computer simulations, and the results are presented. The proposed scheme can easily be implemented without much penalty on hardware, power consumption, and processing time.

Murugesan, S.↗
NASA NTRS1994

David Florida Laboratory Thermal Vacuum Data Processing System

During 1991, the Space Simulation Facility conducted a survey to assess the requirements and analyze the merits for purchasing a new thermal vacuum data processing system for its facilities. A new, integrated, cost effective PC-based system was purchased which uses commercial off-the-shelf software for operation and control. This system can be easily reconfigured and allows its users to access a local area network. In addition, it provides superior performance compared to that of the former system which used an outdated mini-computer and peripheral hardware. This paper provides essential background on the old data processing system's features, capabilities, and the performance criteria that drove the genesis of its successor. This paper concludes with a detailed discussion of the thermal vacuum data processing system's components, features, and its important role in supporting our space-simulation environment and our capabilities for spacecraft testing. The new system was tested during the ANIK E spacecraft test, and was fully operational in November 1991.

Choueiry, Elie↗
NASA NTRS2017

Hardware Interface Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio Ssystem (STRS) Radio

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.

Flight Computer↗
NASA NTRS1981

RAMP - A fault tolerant distributed microcomputer structure for aircraft navigation and control

Design methodologies for realizing future high authority autoflight control systems are being investigated, taking into account also the study of distributed microcomputer architectures. Attention is given to the redundant asynchronous microprocessor (RAMP) structure. RAMP comprises a connected network of microcomputers which has as input command and sensor information, and which generates servo information to drive actuators, and thrust linkages. Tolerance to hardware failures is achieved by static redundancy. Results of a failed microcomputer are simply rejected. This is done in lieu of dynamic redundancy wherein the distributed computer system performs real time fault detection and reconfiguration of the system. Attention is given to the RAMP network structure and operation, flight control with parallel asynchronous computers, and intermittent fault tolerance.

Dunn, W. R.↗
NASA NTRS1988

Development of a space-systems network testbed

This paper describes a communications network testbed which has been designed to allow the development of architectures and algorithms that meet the functional requirements of future NASA communication systems. The central hardware components of the Network Testbed are programmable circuit switching communication nodes which can be adapted by software or firmware changes to customize the testbed to particular architectures and algorithms. Fault detection, isolation, and reconfiguration has been implemented in the Network with a hybrid approach which utilizes features of both centralized and distributed techniques to provide efficient handling of faults within the Network.

Lala, Jaynarayan↗
NASA NTRS2005

Open Architecture SDR for Space

This paper describes an open-architecture SDR (software defined radio) infrastructure that is suitable for space-based operations (Space-SDR). SDR technologies will endow space and planetary exploration systems with dramatically increased capability, reduced power consumption, and significantly less mass than conventional systems, at costs reduced by vigorous competition, hardware commonality, dense integration, reduced obsolescence, interoperability, and software re-use. Significant progress has been recorded on developments like the Joint Tactical Radio System (JSTRS) Software Communication Architecture (SCA), which is oriented toward reconfigurable radios for defense forces operating in multiple theaters of engagement. The JTRS-SCA presents a consistent software interface for waveform development, and facilitates interoperability, waveform portability, software re-use, and technology evolution.

Smith, Carl↗
NASA NTRS2008

STRS Compliant FPGA Waveform Development

The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. Current standards were researched and new standard interfaces were proposed. The implementation of the proposed standard interfaces on a laboratory breadboard SDR will be presented.

Nappier, Jennifer↗
NASA NTRSDate not supplied

Reversionary Control Modes for the Mitigation of Failures in a Partially Turboelectric Aircraft Propulsion System

In support of emission and fuel burn reduction goals, the aviation industry is actively pursuing the advancement of electrified aircraft propulsion (EAP) technology. This includes turboelectric and hybrid electric propulsion designs that combine gas turbine engine and electrical system hardware. Such architectures exhibit a high degree of coupling between subsystems. This drives the need for system-level control strategies to ensure the safe, coordinated, and efficient operation of all subsystems. The design and certification of any aircraft propulsion system requires that all potential subsystem failures are identified, and the hazards posed by these failures are appropriately mitigated. This requirement is particularly challenging for EAP systems due to their integrated nature. One approach to assist in EAP failure mitigation is the inclusion of automated reconfiguration capabilities within the propulsion control system. Such control modes, referred to as reversionary control modes, are designed to automatically detect failures and activate backup control modes upon failure detection. This paper covers the design and evaluation of reversionary control mode logic developed for a partially turboelectric propulsion concept. Test results from a real-time hardware-in-the-loop evaluation of the concept are also presented and discussed. The results show that the developed reversionary control logic can successfully detect and mitigate subsystem failures in a representative environment that includes actual electrical system hardware.

Electrified Aircraft Propulsion↗
NASA NTRSDate not supplied

Reversionary Control Modes for the Mitigation of Failures in a Partially Turboelectric Aircraft Propulsion System

In support of emission and fuel burn reduction goals, the aviation industry is actively pursuing the advancement of electrified aircraft propulsion (EAP) technology. This includes turboelectric and hybrid electric propulsion designs that combine gas turbine engine and electrical system hardware. Such architectures exhibit a high degree of coupling between subsystems. This drives the need for system-level control strategies to ensure the safe, coordinated, and efficient operation of all subsystems. The design and certification of any aircraft propulsion system requires that all potential subsystem failures are identified, and the hazards posed by these failures are appropriately mitigated. This requirement is particularly challenging for EAP systems due to their integrated nature. One approach to assist in EAP failure mitigation is the inclusion of automated reconfiguration capabilities within the propulsion control system. Such control modes, referred to as reversionary control modes, are designed to automatically detect failures and activate backup control modes upon failure detection. This paper covers the design and evaluation of reversionary control mode logic developed for a partially turboelectric propulsion concept. Test results from a real-time hardware-in-the-loop evaluation of the concept are also presented and discussed. The results show that the developed reversionary control logic can successfully detect and mitigate subsystem failures in a representative environment that includes actual electrical system hardware.

Electrified Aircraft Propulsion↗
NASA NTRS2024

Reversionary Control Modes for the Mitigation of Failures in a Partially Turboelectric Aircraft Propulsion System

In support of emission and fuel burn reduction goals, the aviation industry is actively pursuing the advancement of electrified aircraft propulsion (EAP) technology. This includes turboelectric and hybrid electric propulsion designs that combine gas turbine engine and electrical system hardware. Such architectures exhibit a high degree of coupling between subsystems. This drives the need for system-level control strategies to ensure the safe, coordinated, and efficient operation of all subsystems. The design and certification of any aircraft propulsion system requires that all potential subsystem failures are identified, and the hazards posed by these failures are appropriately mitigated. This requirement is particularly challenging for EAP systems due to their integrated nature. One approach to assist in EAP failure mitigation is the inclusion of automated reconfiguration capabilities within the propulsion control system. Such control modes, referred to as reversionary control modes, are designed to automatically detect failures and activate backup control modes upon failure detection. This paper covers the design and evaluation of reversionary control mode logic developed for a partially turboelectric propulsion concept. Test results from a real-time hardware-in-the-loop evaluation of the concept are also presented and discussed. The results show that the developed reversionary control logic can successfully detect and mitigate subsystem failures in a representative environment that includes actual electrical system hardware.

Electrified Aircraft Propulsion↗
NASA NTRS2013

Test Waveform Applications for JPL STRS Operating Environment

This software demonstrates use of the JPL Space Telecommunications Radio System (STRS) Operating Environment (OE), tests APIs (application programming interfaces) presented by JPL STRS OE, and allows for basic testing of the underlying hardware platform. This software uses the JPL STRS Operating Environment ["JPL Space Tele com - munications Rad io System Operating Environment,"(NPO-4776) NASA Tech Briefs, commercial edition, Vol. 37, No. 1 (January 2013), p. 47] to interact with the JPL-SDR Software Defined Radio developed for the CoNNeCT (COmmunications, Navigation, and Networking rEconfigurable Testbed) Project as part of the SCaN Testbed installed on the International Space Station (ISS). These are the first applications that are compliant with the new NASA STRS Architecture Standard. Several example waveform applications are provided to demonstrate use of the JPL STRS OE for the JPL-SDR platform used for the CoNNeCT Project. The waveforms provide a simple digitizer and playback capability for the SBand RF slice, and a simple digitizer for the GPS slice [CoNNeCT Global Positioning System RF Module, (NPO-47764) NASA Tech Briefs, commercial edition, Vol. 36, No. 3 (March 2012), p. 36]. These waveforms may be used for hardware test, as well as for on-orbit or laboratory checkout. Additional example waveforms implement SpaceWire and timer modules, which can be used for time transfer and demonstration of communication between the two Xilinx FPGAs in the JPLSDR. The waveforms are also compatible with ground-based use of the JPL STRS OE on radio breadboards and Linux.

Lux, James P.↗