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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 235 records · Page 13
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Gimballed Shoulders for Friction Stir Welding

In a proposed improvement of tooling for friction stir welding, gimballed shoulders would supplant shoulders that, heretofore, have been fixedly aligned with pins. The proposal is especially relevant to self-reacting friction stir welding. Some definitions of terms, recapitulated from related prior NASA Tech Briefs articles, are prerequisite to a meaningful description of the proposed improvement. In friction stir welding, one uses a tool that includes (1) a rotating shoulder on top (or front) of the workpiece and (2) a pin that rotates with the shoulder and protrudes from the shoulder into the depth of the workpiece. In conventional friction stir welding, the main axial force exerted by the tool on the workpiece is reacted through a ridged backing anvil under (behind) the workpiece. When conventional friction stir welding is augmented with an auto-adjustable pin-tool (APT) capability, the depth of penetration of the pin into the workpiece is varied in real time by a position- or forcecontrol system that extends or retracts the pin as needed to obtain the desired effect. In self-reacting (also known as self-reacted) friction stir welding as practiced heretofore, there are two shoulders: one on top (or front) and one on the bottom (or back) of the workpiece. In this case, a threaded shaft protrudes from the tip of the pin to beyond the back surface of the workpiece. The back shoulder is held axially in place against tension by a nut on the threaded shaft. Both shoulders rotate with the pin and remain aligned coaxially with the pin. The main axial force exerted on the workpiece by the tool and front shoulder is reacted through the back shoulder and the threaded shaft into the friction-stir-welding machine head, so that a backing anvil is no longer needed. A key transmits torque between the bottom shoulder and the threaded shaft, so that the bottom shoulder rotates with the shaft. This concludes the prerequisite definitions of terms.

Carter, Robert↗
NASA NTRS2007

Self-Advancing Step-Tap Drills

Self-advancing tool bits that are hybrids of drills and stepped taps make it possible to form threaded holes wider than about 1/2 in. (about 13 mm) without applying any more axial force than is necessary for forming narrower pilot holes. These self-advancing stepped-tap drills were invented for use by space-suited astronauts performing repairs on reinforced carbon/carbon space-shuttle leading edges during space walks, in which the ability to apply axial drilling forces is severely limited. Self-advancing stepped-tap drills could also be used on Earth for making wide holes without applying large axial forces. A self-advancing stepped-tap drill (see figure) includes several sections having progressively larger diameters, typically in increments between 0.030 and 0.060 in. (between about 0.8 and about 1.5 mm). The tip section, which is the narrowest, is a pilot drill bit that typically has a diameter between 1/8 and 3/16 in. (between about 3.2 and about 4.8 mm). The length of the pilot-drill section is chosen, according to the thickness of the object to be drilled and tapped, so that the pilot hole is completed before engagement of the first tap section. Provided that the cutting-edge geometry of the drill bit is optimized for the material to be drilled, only a relatively small axial force [typically of the order of a few pounds (of the order of 10 newtons)] must be applied during drilling of the pilot hole. Once the first tap section engages the pilot hole, it is no longer necessary for the drill operator to apply axial force: the thread engagement between the tap and the workpiece provides the axial force to advance the tool bit. Like the pilot-drill section, each tap section must be long enough to complete its hole before engagement of the next, slightly wider tap section. The precise values of the increments in diameter, the thread pitch, the rake angle of the tap cutting edge, and other geometric parameters of the tap sections must be chosen, in consideration of the workpiece material and thickness, to prevent stripping of threads during the drilling/tapping operation. A stop-lip or shoulder at the shank end of the widest tap section prevents further passage of the tool bit through the hole.

Pettit, Donald R.↗
NASA NTRS2010

International Space Station Powered Bolt Nut Anomaly and Failure Analysis Summary

A key mechanism used in the on-orbit assembly of the International Space Station (ISS) pressurized elements is the Common Berthing Mechanism (CBM). The mechanism that effects the structural connection of the CBM halves is the Powered Bolt Assembly. There are sixteen Powered Bolt Assemblies per CBM. The CBM has a bolt which engages a self aligning Powered Bolt Nut (PBN) on the mating interface; see Figure 1. The Powered Bolt Assemblies are preloaded to approximately 19 kilo pounds (KIPs) prior to pressurization of the CBM. The PBNs mentioned below, manufactured in 2009, will be used on ISS future missions. An on orbit functional failure of this hardware would be unacceptable and in some instances catastrophic due to the failure of modules to mate and seal the atmosphere, risking loss of crew and ISS functions. The manufacturing processes which create the PBNs need to be strictly controlled. Functional (torque vs. tension) acceptance test failures will be the result of processes not being strictly followed. Without the proper knowledge of thread tolerances, fabrication techniques, and dry film lubricant application processes, PBNs will be, and have been manufactured improperly. The knowledge gained from acceptance test failures and the resolution of those failures, thread fabrication techniques and thread dry film lubrication processes can be applied to many aerospace mechanisms to enhance their performance. Test data and manufactured PBN thread geometry will be discussed for both failed and successfully accepted PBNs.

Sievers, Daniel E.↗
NASA NTRS2007

Advanced Reference Counting Pointers for Better Performance

A computer program implements reference counting pointers (RCPs) that are lock-free, thread-safe, async-safe, and operational on a multiprocessor computer. RCPs are powerful and convenient means of managing heap memory in C++ software. Most prior RCP programs use locks to ensure thread safety and manage concurrency. The present program was developed in a continuing effort to explore ways of using the C++ programming language to develop safety-critical and mission- critical software. This effort includes exploration of lock-free algorithms because they offer potential to avoid some costly and difficult verification problems. Unlike previously published RCP software, the present program does not use locks (meaning that no thread can block progress on another thread): Instead, this program implements algorithms that exploit capabilities of central-processing- unit hardware so as to avoid locks. Once locks are eliminated, it becomes possible to realize the other attributes mentioned in the first sentence. In addition to the abovementioned attributes, this program offers several advantages over other RCP programs that use locks: It is smaller (and, hence, is faster and uses less memory), it is immune to priority inversion, and there is no way for it to cause a C++ exception.

Reinholtz, William↗
NASA NTRS2010

International Space Station Powered Bolt Nut Anomaly and Failure Analysis Summary

A key mechanism used in the on-orbit assembly of the International Space Station (ISS) pressurized elements is the Common Berthing Mechanism. The mechanism that effects the structural connection of the Common Berthing Mechanism halves is the Powered Bolt Assembly. There are sixteen Powered Bolt Assemblies per Common Berthing Mechanism. The Common Berthing Mechanism has a bolt which engages a self aligning Powered Bolt Nut (PBN) on the mating interface (Figure 1). The Powered Bolt Assemblies are preloaded to approximately 84.5 kN (19000 lb) prior to pressurization of the CBM. The PBNs mentioned below, manufactured in 2009, will be used on ISS future missions. An on orbit functional failure of this hardware would be unacceptable and in some instances catastrophic due to the failure of modules to mate and seal the atmosphere, risking loss of crew and ISS functions. The manufacturing processes that create the PBNs need to be strictly controlled. Functional (torque vs. tension) acceptance test failures will be the result of processes not being strictly followed. Without the proper knowledge of thread tolerances, fabrication techniques, and dry film lubricant application processes, PBNs will be, and have been manufactured improperly. The knowledge gained from acceptance test failures and the resolution of those failures, thread fabrication techniques and thread dry film lubrication processes can be applied to many aerospace mechanisms to enhance their performance. Test data and manufactured PBN thread geometry will be discussed for both failed and successfully accepted PBNs.

Sievers, Daniel E.↗
NASA NTRS2008

RACER: Effective Race Detection Using AspectJ

The limits of coding with joint constraints on detected and undetected error rates Programming errors occur frequently in large software systems, and even more so if these systems are concurrent. In the past, researchers have developed specialized programs to aid programmers detecting concurrent programming errors such as deadlocks, livelocks, starvation and data races. In this work we propose a language extension to the aspect-oriented programming language AspectJ, in the form of three new built-in pointcuts, lock(), unlock() and may be Shared(), which allow programmers to monitor program events where locks are granted or handed back, and where values are accessed that may be shared amongst multiple Java threads. We decide thread-locality using a static thread-local objects analysis developed by others. Using the three new primitive pointcuts, researchers can directly implement efficient monitoring algorithms to detect concurrent programming errors online. As an example, we expose a new algorithm which we call RACER, an adoption of the well-known ERASER algorithm to the memory model of Java. We implemented the new pointcuts as an extension to the Aspect Bench Compiler, implemented the RACER algorithm using this language extension and then applied the algorithm to the NASA K9 Rover Executive. Our experiments proved our implementation very effective. In the Rover Executive RACER finds 70 data races. Only one of these races was previously known.We further applied the algorithm to two other multi-threaded programs written by Computer Science researchers, in which we found races as well.

data analysis↗
NASA NTRS2006

Tool for Two Types of Friction Stir Welding

A tool that would be useable in both conventional and self-reacting friction stir welding (FSW) has been proposed. The tool would embody both a prior tooling concept for self-reacting FSW and an auto-adjustable pin-tool (APT) capability developed previously as an augmentation for conventional FSW. Some definitions of terms are prerequisite to a meaningful description of the proposed tool. In conventional FSW, depicted in Figure 1, one uses a tool that includes (1) a rotating shoulder on top (or front) of the workpiece and (2) a rotating pin that protrudes from the shoulder into the depth of the workpiece. The main axial force exerted by the tool on the workpiece is reacted through a ridged backing anvil under (behind) the workpiece. When conventional FSW is augmented with an APT capability, the depth of penetration of the pin into the workpiece is varied in real time by a position- or force-control system that extends or retracts the pin as needed to obtain the desired effect. In self-reacting (also known as self-reacted) friction stir welding (SR-FSW), there are two rotating shoulders: one on top (or front) and one on the bottom (or back) of the workpiece. In this case, a threaded shaft protrudes from the tip of the pin to beyond the back surface of the workpiece. The back shoulder is held axially in place against tension by a nut on the threaded shaft. The main axial force exerted on the workpiece by the tool and front shoulder is reacted through the back shoulder and the threaded shaft, back into the FSW machine head, so that a backing anvil is no longer needed. A key transmits torque between the bottom shoulder and the threaded shaft, so that the bottom shoulder rotates with the shaft. A tool for SRFSW embodying this concept was reported in "Mechanism for Self-Reacted Friction Stir Welding" (MFS-31914), NASA Tech Briefs, Vol. 28, No. 10 (October 2004), page 53. In its outward appearance, the proposed tool (see Figure 2) would fit the above description of an SR-FSW tool. In this case, the FSW machine would have an APT capability and the pin would be modified to accept a bottom shoulder. The APT capability could be used to vary the distance between the front and back shoulders in real time to accommodate process and workpiece-thickness variations. The tool could readily be converted to a conventional FSW tool, with or without APT capability, by simply replacing the modified pin with a conventional FSW pin.

Carter, Robert↗
NASA NTRS2011

XMOS XC-2 Development Board for Mechanical Control and Data Collection

The scanning microwave limb sounder (SMLS) will use technological improvements in low-noise mixers to provide precise data on the Earth s atmospheric composition with high spatial resolution. This project focuses on the design and implementation of a realtime control system needed for airborne engineering tests of the SMLS. The system must coordinate the actuation of optical components using four motors with encoder readback, while collecting synchronized telemetric data from a GPS receiver and 3-axis gyrometric system. A graphical user interface for testing the control system was also designed using Python. Although the system could have been implemented with an FPGA(fieldprogrammable gate array)-based setup, a processor development kit manufactured by XMOS was chosen. The XMOS architecture allows parallel execution of multiple tasks on separate threads, making it ideal for this application. It is easily programmed using XC (a subset of C). The necessary communication interfaces were implemented in software, including Ethernet, with significant cost and time reduction compared to an FPGA-based approach. A simple approach to control the chopper, calibration mirror, and gimbal for the airborne SMLS was needed. The XMOS board allows for multiple threads and real-time data acquisition. The XC-2 development kit is an attractive choice for synchronized, real-time, event-driven applications. The XMOS is based on the transputer microprocessor architecture developed for parallel computing, which is being revamped in this new platform. The XMOS device has multiple cores capable of running parallel applications on separate threads. The threads communicate with each other via user-defined channels capable of transmitting data within the device. XMOS provides a C-based development environment using XC, which eliminates the need for custom tool kits associated with FPGA programming. The XC-2 has four cores and necessary hardware for Ethernet I/O.

Jarnot, Robert F.↗
NASA NTRS2011

Asynchronous Message Service Reference Implementation

This software provides a library of middleware functions with a simple application programming interface, enabling implementation of distributed applications in conformance with the CCSDS AMS (Consultative Committee for Space Data Systems Asynchronous Message Service) specification. The AMS service, and its protocols, implement an architectural concept under which the modules of mission systems may be designed as if they were to operate in isolation, each one producing and consuming mission information without explicit awareness of which other modules are currently operating. Communication relationships among such modules are self-configuring; this tends to minimize complexity in the development and operations of modular data systems. A system built on this model is a society of generally autonomous, inter-operating modules that may fluctuate freely over time in response to changing mission objectives, modules functional upgrades, and recovery from individual module failure. The purpose of AMS, then, is to reduce mission cost and risk by providing standard, reusable infrastructure for the exchange of information among data system modules in a manner that is simple to use, highly automated, flexible, robust, scalable, and efficient. The implementation is designed to spawn multiple threads of AMS functionality under the control of an AMS application program. These threads enable all members of an AMS-based, distributed application to discover one another in real time, subscribe to messages on specific topics, and to publish messages on specific topics. The query/reply (client/server) communication model is also supported. Message exchange is optionally subject to encryption (to support confidentiality) and authorization. Fault tolerance measures in the discovery protocol minimize the likelihood of overall application failure due to any single operational error anywhere in the system. The multi-threaded design simplifies processing while enabling application nodes to operate at high speeds; linked lists protected by mutex semaphores and condition variables are used for efficient, inter-thread communication. Applications may use a variety of transport protocols underlying AMS itself, including TCP (Transmission Control Protocol), UDP (User Datagram Protocol), and message queues.

Burleigh, Scott C.↗
NASA NTRS2010

Symbolic Analysis of Concurrent Programs with Polymorphism

The current trend of multi-core and multi-processor computing is causing a paradigm shift from inherently sequential to highly concurrent and parallel applications. Certain thread interleavings, data input values, or combinations of both often cause errors in the system. Systematic verification techniques such as explicit state model checking and symbolic execution are extensively used to detect errors in such systems [7, 9]. Explicit state model checking enumerates possible thread schedules and input data values of a program in order to check for errors [3, 9]. To partially mitigate the state space explosion from data input values, symbolic execution techniques substitute data input values with symbolic values [5, 7, 6]. Explicit state model checking and symbolic execution techniques used in conjunction with exhaustive search techniques such as depth-first search are unable to detect errors in medium to large-sized concurrent programs because the number of behaviors caused by data and thread non-determinism is extremely large. We present an overview of abstraction-guided symbolic execution for concurrent programs that detects errors manifested by a combination of thread schedules and data values [8]. The technique generates a set of key program locations relevant in testing the reachability of the target locations. The symbolic execution is then guided along these locations in an attempt to generate a feasible execution path to the error state. This allows the execution to focus in parts of the behavior space more likely to contain an error.

Rungta, Neha Shyam↗
NASA NTRS2016

Mounting Systems for Structural Members, Fastening Assemblies Thereof, and Vibration Isolation Systems Including the Same

Mounting systems for structural members, fastening assemblies thereof, and vibration isolation systems including the same are provided. Mounting systems comprise a pair of mounting brackets, each clamped against a fastening assembly forming a mounting assembly. Fastening assemblies comprise a spherical rod end comprising a spherical member having a through opening and an integrally threaded shaft, first and second seating members on opposite sides of the spherical member and each having a through opening that is substantially coaxial with the spherical member through opening, and a partially threaded fastener that threadably engages each mounting bracket forming the mounting assembly. Structural members have axial end portions, each releasably coupled to a mounting bracket by the integrally threaded shaft. Axial end portions are threaded in opposite directions for permitting structural member rotation to adjust a length thereof to a substantially zero strain position. Structural members may be vibration isolator struts in vibration isolation systems.

Young, Ken↗
NASA NTRS2024

Disentangling the Entangled Linkages of Magnetic Helicity

Magnetic helicity, H, measures magnetic linkages in a volume. The early theoretical development of helicity focused on magnetically closed systems in V bounded by ∂V. For magnetically closed systems, V ∈ R -3 = V + V∗, no magnetic flux threads the boundary, n̂ · B|∂V = 0. Berger & Field (1984) and Finn & Antonsen (1985) extended the definition of helicity to relative helicity, H, for magnetically open systems where magnetic flux may thread the boundary. Berger (1999, 2003) expressed this relative helicity as two gauge invariant terms that describe the self helicity of magnetic field that closes inside V and the mutual helicity between the magnetic field that threads the boundary ∂V and the magnetic field that closes inside V. The total magnetic field that permeates V entangles magnetic fields that are produced by current sources J in V with magnetic fields that are produced by current sources J∗ in V∗. Building on this fact, we extend Berger’s expressions for relative magnetic helicity to eight gauge invariant quantities that simultaneously characterize both of these self and mutual helicities and attribute their origins to currents J in V and/or J∗ in V∗, thereby disentangling the domain of origin for these entangled linkages. We arrange these eight terms into novel expressions for internal and external helicity (self) and internal-external helicity (mutual) based on their domain of origin. The implications of these linkages for interpreting magnetic energy is discussed and new boundary observables are proposed for tracking the evolution of the field that threads the boundary.

Analytical mathematics↗
DOE OSTI2020

Prioritizing local and remote memory access in a non-uniform memory access architecture

A miss in a cache by a thread in a wavefront is detected. The wavefront includes a plurality of threads that are executing a memory access request concurrently on a corresponding plurality of processor cores. A priority is assigned to the thread based on whether the memory access request is addressed to a local memory or a remote memory. The memory access request for the thread is performed based on the priority. In some cases, the cache is selectively bypassed depending on whether the memory access request is addressed to the local or remote memory. A cache block is requested in response to the miss. The cache block is biased towards a least recently used position in response to requesting the cache block from the local memory and towards a most recently used position in response to requesting the cache block from the remote memory.

Boyer, Michael W.↗
DOE OSTI2024

Integrated solution techniques for security constrained unit commitment problem

Apparatus and methods are disclosed for solving Mixed Integer Programming (MIP) problems, such as Security Constrained Unit Commitment (SCUC) problems used by power grid authorities to perform day-ahead market clearing. In certain examples, a plurality of threads of a software tool implementing a concurrent optimizer can be executed concurrently and sequentially to generate new solutions to a SCUC problem for an upcoming planning horizon. Data can be shared among the concurrently executing threads, such as intermediate/incumbent solutions and hints regarding the fixing of variables and constraints to reduce the size of the SCUC problem. In some examples, the threads are seeded with historical solutions from prior planning horizons. The software tool can select a best solution from the solutions generated by the threads, and determine dispatch instructions for a device coupled to the power grid for the upcoming planning horizon based at least in part on the selected solution.

Pan, Feng↗
DOE OSTI2024

Development of Real-Time High-Density Pulsar Data Transmission and Processing for Grid Synchronization

Taking advantage of the extreme stability of the pulsar period, it can serve as the timing source for grid synchronization to compensate for the timing drift instigated by the loss of GPS signal. Nevertheless, the real-time transmission and processing of the pulsar data suffer from its high-frequency data rate, varying from megahertz to gigahertz, resulting in reduced computing speed and increased time delay. To mitigate this issue, the hardware and software frameworks are implemented for the high-density pulsar data transmission and processing for grid synchronization in this research. Initially, the high-density pulsar data is transferred using open-source software. The complementary duty cycle timing module is designed to coordinate the operation of the dual-channel high-speed interface and software. Subsequently, the multiple-threading is applied to the receiving, parsing, and splicing pulsar data. Next, the pulsar signal extraction method is implemented based on the polyphase filterbank and time of arrival estimation. Ultimately, real-time performance verification experiments are carried out for different components under two hardware platforms. Finally, the results demonstrate that only 0.482 s is required for processing 4 Gigabyte data through multiple-threading, which is 3.8 times faster than the single thread. The pulsar signal extraction can also be executed within 707 ms for 4.8 seconds of data, thereby indicating that real-time requirements can be met.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

Investigation of defect formation at the early stage of PVT-grown 4H-SiC crystals

Here, several 4° off-axis 4H-SiC wafers with several hundred microns of initial-stage growth by PVT method are investigated by Synchrotron Monochromatic Beam X-ray Topography (SMBXT). Defect behavior across the seed/newly grown layer interface are demonstrated. Comparison of early stage grown layers to seed sample indicates generation of threading edge dislocation (TED) and threading screw dislocation (TSD)/ threading mixed dislocation (TMD) pairs at the interface while most basal plane dislocations (BPDs) are deflected into TEDs. The (0001) facet of the crystal is already formed at early stage growth at the edge of the wafer and high nitrogen incorporation in facet leads to conditions favorable for nucleation and glide of Shockley/double Shockley faults with layers of 3C-SiC deposited on facet acting as nuclei. Unique-shaped dislocations are observed at early stage growth, which are caused by deflection of TSDs/TMDs and TEDs by macrosteps near the periphery of the sample and the subsequent glide of the a components. The effect of the quality of the seed surface before growth is manifested as randomly oriented arrays of pairs of TEDs and TSDs/TMDs on the as grown surface resulting from residual surface damage from scratches.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Interband cascade light-emitting diodes grown on silicon substrates using GaSb buffer layer

Interband cascade light-emitting diodes (ICLEDs) offer attractive advantages for infrared applications, which would greatly expand if high-quality growth on silicon substrates could be achieved. Here, this work describes the formation of threading dislocations in ICLEDs grown monolithically on GaSb-on-Silicon wafers. The epitaxial growth is done in two stages: the GaSb-on-Silicon buffer is grown first, followed by the ICLED growth. The buffer growth involves the nucleation of a 10-nm-thick AlSb buffer layer on the silicon surface, followed by the GaSb growth. The AlSb nucleation layer promotes the formation of 90° and 60° interfacial misfit dislocations, resulting in a highly planar morphology for subsequent GaSb growth that is almost 100% relaxed. The resulting GaSb buffer for growth of the ICLED has a threading dislocation density of ~10 7 /cm 2 after ~3 μm of growth. The fabricated LEDs showed variations in device performance, with some devices demonstrating comparable light–current–voltage curves to those for devices grown on GaSb substrates, while other devices showed somewhat reduced relative performance. Cross-sectional transmission electron microscopy observations of the inferior diodes indicated that the multiplication of threading dislocations in the active region had most likely caused the increased leakage current and lower output power. Enhanced defect filter layers on the GaSb/Si substrates should provide more consistent diode performance and a viable future growth approach for antimonide-based ICLEDs and other infrared devices.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Automated Hybrid Variance Reduction on Advanced Architectures in the Shift Monte Carlo Code

Monte Carlo transport methods are the most accurate schemes for solving problems with complex energy and spatial features, but they come with a high computational cost. Although hybrid methods have enabled the use of Monte Carlo transport for a large class of problems, they still require significant computing resources. Modern multicore CPUs with large numbers of compute cores and graphical processing units (GPUs) provide opportunities to optimize the memory and run-time costs of hybrid Monte Carlo methods. This paper documents the development and analysis of three Monte Carlo transport algorithms that support hybrid transport using the consistent adjoint-driven importance sampling (CADIS) and forward-weighted CADIS methods in the Shift Monte Carlo code: history-based transport using static and dynamic threading on multicore CPUs and event-based transport enabling weight window tracking on GPUs. The results are shown for two challenging hybrid problems on the Frontier supercomputer at the Oak Ridge Leadership Computing Facility. The results show that all three methods yield good performance and enable solutions of difficult fixed-source transport problems in less than 2 min on 20 nodes of Frontier. Dynamic threading was observed to give up to 20% better scaling behavior than static threading. Moreover, the AMD Instinct 250X GPU was found to give 9 to 11 times greater throughput per graphics compute die than the best CPU performance. In conclusion, additional opportunities for optimization of hybrid transport on GPUs are discussed.

Denovo↗