Results for “CIRCUIT” — Page 14

NASA NTRS1990

Integrated circuit reliability testing

A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

Buehler, Martin G.↗

NASA NTRS1976

Sense circuit arrangement

A unique, two-node sense circuit is disclosed. The circuit includes a bridge comprised of resistance elements and a differential amplifier. The two-node circuit is suitably adapted to be arranged in an array comprised of a plurality of discrete bridge-amplifiers which can be selectively energized. The circuit is arranged so as to form a configuration with minimum power utilization and a reduced number of components and interconnections therebetween.

Bohning, Oliver D.↗

NASA NTRS2008

Chemical Detection using Electrically Open Circuits having no Electrical Connections

This paper presents investigations to date on chemical detection using a recently developed method for designing, powering and interrogating sensors as electrically open circuits having no electrical connections. In lieu of having each sensor from a closed circuit with multiple electrically connected components, an electrically conductive geometric pattern that is powered using oscillating magnetic fields and capable of storing an electric field and a magnetic field without the need of a closed circuit or electrical connections is used. When electrically active, the patterns respond with their own magnetic field whose frequency, amplitude and bandwidth can be correlated with the magnitude of the physical quantities being measured. Preliminary experimental results of using two different detection approaches will be presented. In one method, a thin film of a reactant is deposited on the surface of the open-circuit sensor. Exposure to a specific targeted reactant shifts the resonant frequency of the sensor. In the second method, a coating of conductive material is placed on a thin non-conductive plastic sheet that is placed over the surface of the sensor. There is no physical contact between the sensor and the electrically conductive material. When the conductive material is exposed to a targeted reactant, a chemical reaction occurs that renders the material non-conductive. The change in the material s electrical resistance within the magnetic field of the sensor alters the sensor s response bandwidth and amplitude, allowing detection of the reaction without having the reactants in physical contact with the sensor.

Woodward, Stanley E.↗

NASA NTRS2008

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

Phillips, Thomas A.↗

NASA NTRS2005

Transistor Level Circuit Experiments using Evolvable Hardware

The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

self configuration↗

NASA NTRS2009

Circuit for Driving Piezoelectric Transducers

The figure schematically depicts an oscillator circuit for driving a piezoelectric transducer to excite vibrations in a mechanical structure. The circuit was designed and built to satisfy application-specific requirements to drive a selected one of 16 such transducers at a regulated amplitude and frequency chosen to optimize the amount of work performed by the transducer and to compensate for both (1) temporal variations of the resonance frequency and damping time of each transducer and (2) initially unknown differences among the resonance frequencies and damping times of different transducers. In other words, the circuit is designed to adjust itself to optimize the performance of whichever transducer is selected at any given time. The basic design concept may be adaptable to other applications that involve the use of piezoelectric transducers in ultrasonic cleaners and other apparatuses in which high-frequency mechanical drives are utilized. This circuit includes three resistor-capacitor networks that, together with the selected piezoelectric transducer, constitute a band-pass filter having a peak response at a frequency of about 2 kHz, which is approximately the resonance frequency of the piezoelectric transducers. Gain for generating oscillations is provided by a power hybrid operational amplifier (U1). A junction field-effect transistor (Q1) in combination with a resistor (R4) is used as a voltage-variable resistor to control the magnitude of the oscillation. The voltage-variable resistor is part of a feedback control loop: Part of the output of the oscillator is rectified and filtered for use as a slow negative feedback to the gate of Q1 to keep the output amplitude constant. The response of this control loop is much slower than 2 kHz and, therefore, does not introduce significant distortion of the oscillator output, which is a fairly clean sine wave. The positive AC feedback needed to sustain oscillations is derived from sampling the current through the piezoelectric transducer. This positive AC feedback, in combination with the slow feedback to the voltage-variable resistors, causes the overall loop gain to be just large enough to keep the oscillator running. The positive feedback loop includes two 16-channel multiplexers, which are not shown in the figure. One multiplexer is used to select the desired piezoelectric transducer. The other multiplexer, which is provided for use in the event that there are significant differences among the damping times of the 16 piezoelectric transducers, facilitates changing the value of one of the resistors in the positive-feedback loop to accommodate the damping time of the selected transducer.

Randall, David P.↗

NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗

NASA NTRS2010

Solar cell circuit and method for manufacturing solar cells

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Mardesich, Nick↗

NASA NTRS2010

Estimating the Probability of Electrical Short Circuits from Tin Whiskers

To comply with lead-free legislation, many manufacturers have converted from tin-lead to pure tin finishes of electronic components. However, pure tin finishes have a greater propensity to grow tin whiskers than tin-lead finishes. Since tin whiskers present an electrical short circuit hazard in electronic components, simulations have been developed to quantify the risk of said short circuits occurring. Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that had an unknown probability associated with it. Note however that due to contact resistance electrical shorts may not occur at lower voltage levels. In our first article we developed an empirical probability model for tin whisker shorting. In this paper, we develop a more comprehensive empirical model using a refined experiment with a larger sample size, in which we studied the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From the resulting data we estimated the probability distribution of an electrical short, as a function of voltage. In addition, the unexpected polycrystalline structure seen in the focused ion beam (FIB) cross section in the first experiment was confirmed in this experiment using transmission electron microscopy (TEM). The FIB was also used to cross section two card guides to facilitate the measurement of the grain size of each card guide's tin plating to determine its finish .

Courey, Karim J.↗

NASA NTRS2006

Compact, Efficient Drive Circuit for a Piezoelectric Pump

A switching circuit that drives a piezoelectric pump at a high voltage with a polarity that alternates at the desired mechanical pump frequency is described and depicted. This circuit offers advantages of (1) high energy efficiency relative to conventional direct-drive circuits and (2) compactness relative to conventional resonant drive circuits.

Matice, Chris↗

NASA NTRS2005

Stripline/Microstrip Transition in Multilayer Circuit Board

A stripline-to-microstrip transition has been incorporated into a multilayer circuit board that supports a distributed solid-state microwave power amplifier, for the purpose of coupling the microwave signal from a buried-layer stripline to a top-layer microstrip. The design of the transition could be adapted to multilayer circuit boards in such products as cellular telephones (for connecting between circuit-board signal lines and antennas), transmitters for Earth/satellite communication systems, and computer mother boards (if processor speeds increase into the range of tens of gigahertz). The transition is designed to satisfy the following requirements in addition to the basic coupling requirement described above: (1) The transition must traverse multiple layers, including intermediate layers that contain DC circuitry. (2) The transition must work at a frequency of 32 GHz with low loss and low reflection. (3) The power delivered by the transition to top-layer microstrip must be split equally in opposite directions along the microstrip. Referring to the figure, this amounts to a requirement that when power is supplied to input port 1, equal amounts of power flow through output ports 2 and 3. (4) The signal-line via that is necessarily a part of such a transition must not be what is known in the art as a blind via; that is, it must span the entire thickness of the circuit board.

Epp, Larry↗

NASA NTRS2012

Multi-Layer E-Textile Circuits

Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

Dunne, Lucy E.↗

NASA NTRS2009

Estimating the Probability of Electrical Short Circuits from Tin Whiskers

To comply with lead-free legislation, many manufacturers have converted from tin-lead to pure tin finishes of electronic components. However, pure tin finishes have a greater propensity to grow tin whiskers than tin-lead finishes. Since tin whiskers present an electrical short circuit hazard in electronic components, simulations have been developed to quantify the risk of said short circuits occurring. Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that had an unknown probability associated with it. Note however that due to contact resistance electrical shorts may not occur at lower voltage levels. In our first article we developed an empirical probability model for tin whisker shorting. In this paper, we develop a more comprehensive empirical model using a refined experiment with a larger sample size, in which we studied the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From the resulting data we estimated the probability distribution of an electrical short, as a function of voltage.

Courey, Karim J.↗

NASA NTRS2009

Developing an Empirical Model for Estimating the Probability of Electrical Short Circuits from Tin Whiskers

To comply with lead-free legislation, many manufacturers have converted from tin-lead to pure tin finishes of electronic components. However, pure tin finishes have a greater propensity to grow tin whiskers than tin-lead finishes. Since tin whiskers present an electrical short circuit hazard in electronic components, simulations have been developed to quantify the risk of said short circuits occurring. Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that had an unknown probability associated with it. Note however that due to contact resistance electrical shorts may not occur at lower voltage levels. In our first article we developed an empirical probability model for tin whisker shorting. In this paper, we develop a more comprehensive empirical model using a refined experiment with a larger sample size, in which we studied the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From the resulting data we estimated the probability distribution of an electrical short, as a function of voltage. In addition, the unexpected polycrystalline structure seen in the focused ion beam (FIB) cross section in the first experiment was confirmed in this experiment using transmission electron microscopy (TEM). The FIB was also used to cross section two card guides to facilitate the measurement of the grain size of each card guide's tin plating to determine its finish.

Courey, Karim J.↗

NASA NTRS2013

Fast, High-Precision Readout Circuit for Detector Arrays

The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.

Rider, David M.↗

NASA NTRS2014

5.8kV SiC PiN Diode for Switching of High-Efficiency Inductive Pulsed Plasma Thruster Circuits

Inductive Pulsed Plasma Thruster (IPPT) pulse circuits, such as those needed to operate the Pulsed Inductive Thruster (PIT), are required to quickly switch capacitor banks operating at a period of μs while conducting current at levels on the order of at least 10 kA. [1,2] For all iterations of the PIT to date, spark gaps have been used to discharge the capacitor bank through an inductive coil. Recent availability of fast, high‐power solid state switching devices makes it possible to consider the use of semiconductor switches in modern IPPTs. In addition, novel pre‐ionization schemes have led to a reduction in discharge energy per pulse for electric thrusters of this type, relaxing the switching requirements for these thrusters. [3,4] Solid state switches offer the advantage of greater controllability and reliability, as well as decreased drive circuit dimensions and mass relative to spark gap switches. The use of solid state devices such as Integrated Gate Bipolar Transistors (IGBTs), Gate Turn‐off Thyristors (GTOs) and Silicon‐Controlled Rectifiers (SCRs) often involves the use of power diodes. These semiconductor devices may be connected antiparallel to the switch for protection from reverse current, or used to reduce power loss in a circuit by clamping off current ringing. In each case, higher circuit efficiency may be achieved by using a diode that is able to transition, or 'switch,' from the forward conducting state ('on' state) to the reverse blocking state ('off' state) in the shortest amount of time, thereby minimizing current ringing and switching losses. Silicon Carbide (SiC) PiN diodes offer significant advantages to conventional fast‐switching Silicon (Si) diodes for high power and fast switching applications. A wider band gap results in a breakdown voltage 10 times that of Si, so that a SiC device may have a thinner drift region for a given blocking voltage. [5] This leads to smaller, lighter devices for high voltage applications, as well as reduced forward conduction losses, faster reverse recovery time (faster turn‐off), and lower‐magnitude reverse recovery current. In addition, SiC devices have lower leakage current as compared to their Si counterparts, and a high thermal conductivity, potentially allowing the former to operate at higher temperatures with a smaller, lighter heatsink (or no heatsink at all).

Toftul, Alexandra↗

NASA NTRS2016

Sampling and Control Circuit Board for an Inertial Measurement Unit

A circuit board that serves as a control and sampling interface to an inertial measurement unit ("IMU") is provided. The circuit board is also configured to interface with a local oscillator and an external trigger pulse. The circuit board is further configured to receive the external trigger pulse from an external source that time aligns the local oscillator and initiates sampling of the inertial measurement device for data at precise time intervals based on pulses from the local oscillator. The sampled data may be synchronized by the circuit board with other sensors of a navigation system via the trigger pulse.

Chelmins, David T↗

NASA NTRS2016

Vibration Damping Circuit Card Assembly

A vibration damping circuit card assembly includes a populated circuit card having a mass M. A closed metal container is coupled to a surface of the populated circuit card at approximately a geometric center of the populated circuit card. Tungsten balls fill approximately 90% of the metal container with a collective mass of the tungsten balls being approximately (0.07) M.

Hunt, Ronald Allen↗