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At least 253 records · Page 14

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NASA NTRS2005

CHARGING OF DEVICES BY MICROWAVE POWER BEAMING

A system for providing wireless, charging power and/or primary power to electronic/electrical devices is described whereby microwave energy is employed. Microwave energy is focused by a power transmitter comprising one or more adaptively-phased microwave array emitters onto a device to be charged. Rectennas within the device to be charged receive and rectify the microwave energy and use it for battery charging and/or for primary power. A locator signal generated by the device to be charged is analyzed by the system to determine the location of the device to be charged relative to the microwave array emitters, permitting thc microwave energy to be directly specifically towards the device to be charged. Backscatter detectors respond to backscatter energy reflected off of any obstacle between the device to be charged and the microwave array emitters. Power to any obstructed microwave array emitter is reduced until the obstruction is removed. Optionally, data can be modulated onto microwave energy beams produced by the array emitter and demodulated by the device, thereby providing means of data communication from the power transmitter to the device. Similarly, data can be modulated onto the locator signal and demodulated in the power transmitter, thereby providing means of data communication from the device to the power transmitter.

Landis, Geoffrey A.↗

NASA NTRS2002

Microgyroscope with closed loop output

A micro-gyroscope (10) having closed loop operation by a control voltage (V.sub.TY), that is demodulated by an output signal of the sense electrodes (S1, S2), providing Coriolis torque rebalance to prevent displacement of the micro-gyroscope (10) on the output axis (y-axis). The present invention provides wide-band, closed-loop operation for a micro-gyroscope (10) and allows the drive frequency to be closely tuned to a high Q sense axis resonance. A differential sense signal (S1-S2) is compensated and fed back by differentially changing the voltage on the drive electrodes to rebalance Coriolis torque. The feedback signal is demodulated in phase with the drive axis signal (K.sub..omega..crclbar..sub.x) to produce a measure of the Coriolis force.

Challoner, A. Dorian↗

NASA NTRS2008

Fast Offset Laser Phase-Locking System

Figure 1 shows a simplified block diagram of an improved optoelectronic system for locking the phase of one laser to that of another laser with an adjustable offset frequency specified by the user. In comparison with prior systems, this system exhibits higher performance (including higher stability) and is much easier to use. The system is based on a field-programmable gate array (FPGA) and operates almost entirely digitally; hence, it is easily adaptable to many different systems. The system achieves phase stability of less than a microcycle. It was developed to satisfy the phase-stability requirement for a planned spaceborne gravitational-wave-detecting heterodyne laser interferometer (LISA). The system has potential terrestrial utility in communications, lidar, and other applications. The present system includes a fast phasemeter that is a companion to the microcycle-accurate one described in High-Accuracy, High-Dynamic-Range Phase-Measurement System (NPO-41927), NASA Tech Briefs, Vol. 31, No. 6 (June 2007), page 22. In the present system (as in the previously reported one), beams from the two lasers (here denoted the master and slave lasers) interfere on a photodiode. The heterodyne photodiode output is digitized and fed to the fast phasemeter, which produces suitably conditioned, low-latency analog control signals which lock the phase of the slave laser to that of the master laser. These control signals are used to drive a thermal and a piezoelectric transducer that adjust the frequency and phase of the slave-laser output. The output of the photodiode is a heterodyne signal at the difference between the frequencies of the two lasers. (The difference is currently required to be less than 20 MHz due to the Nyquist limit of the current sampling rate. We foresee few problems in doubling this limit using current equipment.) Within the phasemeter, the photodiode-output signal is digitized to 15 bits at a sampling frequency of 40 MHz by use of the same analog-to-digital converter (ADC) as that of the previously reported phasemeter. The ADC output is passed to the FPGA, wherein the signal is demodulated using a digitally generated oscillator signal at the offset locking frequency specified by the user. The demodulated signal is low-pass filtered, decimated to a sample rate of 1 MHz, then filtered again. The decimated and filtered signal is converted to an analog output by a 1 MHz, 16-bit digital-to-analog converters. After a simple low-pass filter, these analog signals drive the thermal and piezoelectric transducers of the laser.

Shaddock, Daniel↗

NASA NTRS2011

Fiber-Optic Magnetic-Field-Strength Measurement System for Lightning Detection

A fiber-optic sensor system is designed to measure magnetic fields associated with a lightning stroke. Field vector magnitudes are detected and processed for multiple locations. Since physical limitations prevent the sensor elements from being located in close proximity to highly conductive materials such as aluminum, the copper wire sensor elements (3) are located inside a 4-cubic-in. (.66-cubic-cm) plastic housing sensor head and connected to a fiber-optic conversion module by shielded cabling, which is limited to the shortest length feasible. The signal path between the conversion module and the avionics unit which processes the signals are fiber optic, providing enhanced immunity from electromagnetic radiation incident in the vicinity of the measurements. The sensors are passive, lightweight, and much smaller than commercial B-dot sensors in the configuration which measures a three-dimensional magnetic field. The system is expandable, and provides a standard-format output signal for downstream processing. Inside of the sensor head, three small search coils, each having a few turns on a circular form, are mounted orthogonally inside the non-metallic housing. The fiber-optic conversion module comprises three interferometers, one for each search coil. Each interferometer has a high bandwidth optical phase modulator that impresses the signal received from its search coil onto its output. The output of each interferometer travels by fiber optic cable to the avionics unit, and the search coil signal is recovered by an optical phase demodulator. The output of each demodulator is fed to an analog-to-digital converter, whose sampling rate is determined by the maximum expected rate of rise and peak signal magnitude. The output of the digital processor is a faithful reproduction of the coil response to the incident magnetic field. This information is provided in a standard output format on a 50-ohm port that can be connected to any number of data collection and processing instruments and/or systems. The measurement of magnetic fields using fiber-optic signal processing is novel because it eliminates limitations of a traditional B-dot system. These limitations include the distance from the sensor to the measurement device, the potential for the signal to degrade or be corrupted by EMI from lightning, and the size and weight of the sensor and associated plate.

Gurecki, Jay↗

NASA NTRS2006

Receiver Would Control Phasing of a Phased-Array Antenna

In a proposed digital signal-processing technique, a radio receiver would control the phasing of a phased-array antenna to aim the peaks of the antenna radiation pattern toward desired signal sources while aiming the nulls of the pattern toward interfering signal sources. The technique was conceived for use in a Global Positioning System (GPS) receiver, for which the desired signal sources would be GPS satellites and typical interference sources would be terrestrial objects that cause multipath propagation. The technique could also be used to optimize reception in spread-spectrum cellular-telephone and military communication systems. During reception of radio signals in a conventional phased-array antenna system, received signals at their original carrier frequencies are phase-shifted, then combined by analog circuitry. The combination signal is then subjected to down-conversion and demodulation. In a system according to the proposed technique (see figure), the signal received by each antenna would be subjected to down-conversion, spread-spectrum demodulation, and correlation; this processing would be performed separately from, and simultaneously with, similar processing of signals received by the other antenna elements. Following analog down-conversion to baseband, the signals would be digitized, and all subsequent processing would be digital. In the digital process, residual carriers would be removed and each signal would be correlated with a locally generated model pseudorandum-noise code, all following normal GPS procedure. As part of this procedure, accumulated values would be added in software and the resulting signals would be phase-shifted in software by the amounts necessary to synthesize the desired antenna directional gain pattern of peaks and nulls. The principal advantage of this technique over the conventional radio-frequency-combining technique is that the parallel digital baseband processing of the signals from the various antenna elements would be a relatively inexpensive and flexible means for exploiting the inherent multiple-peak/multiple-null aiming capability of a phased-array antenna. In the original intended GPS application, the peaks and nulls could be directed independently for each GPS signal being tracked by the GPS receiver. The technique could also be applied to other code-division multiple-access communication systems.

Dunn, Charles E.↗

NASA NTRS2012

Downsampling Photodetector Array with Windowing

In a photon counting detector array, each pixel in the array produces an electrical pulse when an incident photon on that pixel is detected. Detection and demodulation of an optical communication signal that modulated the intensity of the optical signal requires counting the number of photon arrivals over a given interval. As the size of photon counting photodetector arrays increases, parallel processing of all the pixels exceeds the resources available in current application-specific integrated circuit (ASIC) and gate array (GA) technology; the desire for a high fill factor in avalanche photodiode (APD) detector arrays also precludes this. Through the use of downsampling and windowing portions of the detector array, the processing is distributed between the ASIC and GA. This allows demodulation of the optical communication signal incident on a large photon counting detector array, as well as providing architecture amenable to algorithmic changes. The detector array readout ASIC functions as a parallel-to-serial converter, serializing the photodetector array output for subsequent processing. Additional downsampling functionality for each pixel is added to this ASIC. Due to the large number of pixels in the array, the readout time of the entire photodetector is greater than the time between photon arrivals; therefore, a downsampling pre-processing step is done in order to increase the time allowed for the readout to occur. Each pixel drives a small counter that is incremented at every detected photon arrival or, equivalently, the charge in a storage capacitor is incremented. At the end of a user-configurable counting period (calculated independently from the ASIC), the counters are sampled and cleared. This downsampled photon count information is then sent one counter word at a time to the GA. For a large array, processing even the downsampled pixel counts exceeds the capabilities of the GA. Windowing of the array, whereby several subsets of pixels are designated for processing, is used to further reduce the computational requirements. The grouping of the designated pixel frame as the photon count information is sent one word at a time to the GA, the aggregation of the pixels in a window can be achieved by selecting only the designated pixel counts from the serial stream of photon counts, thereby obviating the need to store the entire frame of pixel count in the gate array. The pixel count se quence from each window can then be processed, forming lower-rate pixel statistics for each window. By having this processing occur in the GA rather than in the ASIC, future changes to the processing algorithm can be readily implemented. The high-bandwidth requirements of a photon counting array combined with the properties of the optical modulation being detected by the array present a unique problem that has not been addressed by current CCD or CMOS sensor array solutions.

Patawaran, Ferze D.↗

NASA NTRS2012

Sample-Clock Phase-Control Feedback

To demodulate a communication signal, a receiver must recover and synchronize to the symbol timing of a received waveform. In a system that utilizes digital sampling, the fidelity of synchronization is limited by the time between the symbol boundary and closest sample time location. To reduce this error, one typically uses a sample clock in excess of the symbol rate in order to provide multiple samples per symbol, thereby lowering the error limit to a fraction of a symbol time. For systems with a large modulation bandwidth, the required sample clock rate is prohibitive due to current technological barriers and processing complexity. With precise control of the phase of the sample clock, one can sample the received signal at times arbitrarily close to the symbol boundary, thus obviating the need, from a synchronization perspective, for multiple samples per symbol. Sample-clock phase-control feedback was developed for use in the demodulation of an optical communication signal, where multi-GHz modulation bandwidths would require prohibitively large sample clock frequencies for rates in excess of the symbol rate. A custom mixedsignal (RF/digital) offset phase-locked loop circuit was developed to control the phase of the 6.4-GHz clock that samples the photon-counting detector output. The offset phase-locked loop is driven by a feedback mechanism that continuously corrects for variation in the symbol time due to motion between the transmitter and receiver as well as oscillator instability. This innovation will allow significant improvements in receiver throughput; for example, the throughput of a pulse-position modulation (PPM) with 16 slots can increase from 188 Mb/s to 1.5 Gb/s.

Quirk, Kevin J.↗

NASA NTRS2013

Software Defined Radio with Parallelized Software Architecture

This software implements software-defined radio procession over multicore, multi-CPU systems in a way that maximizes the use of CPU resources in the system. The software treats each processing step in either a communications or navigation modulator or demodulator system as an independent, threaded block. Each threaded block is defined with a programmable number of input or output buffers; these buffers are implemented using POSIX pipes. In addition, each threaded block is assigned a unique thread upon block installation. A modulator or demodulator system is built by assembly of the threaded blocks into a flow graph, which assembles the processing blocks to accomplish the desired signal processing. This software architecture allows the software to scale effortlessly between single CPU/single-core computers or multi-CPU/multi-core computers without recompilation. NASA spaceflight and ground communications systems currently rely exclusively on ASICs or FPGAs. This software allows low- and medium-bandwidth (100 bps to approx.50 Mbps) software defined radios to be designed and implemented solely in C/C++ software, while lowering development costs and facilitating reuse and extensibility.

Heckler, Greg↗

NASA NTRS2013

Software Defined Radio with Parallelized Software Architecture

This software implements software-defined radio procession over multi-core, multi-CPU systems in a way that maximizes the use of CPU resources in the system. The software treats each processing step in either a communications or navigation modulator or demodulator system as an independent, threaded block. Each threaded block is defined with a programmable number of input or output buffers; these buffers are implemented using POSIX pipes. In addition, each threaded block is assigned a unique thread upon block installation. A modulator or demodulator system is built by assembly of the threaded blocks into a flow graph, which assembles the processing blocks to accomplish the desired signal processing. This software architecture allows the software to scale effortlessly between single CPU/single-core computers or multi-CPU/multi-core computers without recompilation. NASA spaceflight and ground communications systems currently rely exclusively on ASICs or FPGAs. This software allows low- and medium-bandwidth (100 bps to .50 Mbps) software defined radios to be designed and implemented solely in C/C++ software, while lowering development costs and facilitating reuse and extensibility.

Heckler, Greg↗

NASA NTRS2018

Microwave Radar Sensor Modules

Systems and methods for detecting biometrics using microwave radar sensor modules are disclosed. Integrated microwave sensor modules can include a transmitter unit configured to generate at least one continuous wave transmit signal based upon at least one frequency control signal, a receiver unit configured to utilize a cancellation path to cancel contributions to a return signal based upon at least one cancellation path control signal, and a microcontroller unit that includes a processor, a memory containing a microcontroller application, where the microcontroller application configures the processor to generate at least one frequency control signal to generate least one CW transmit signal having a plurality of frequencies, generate at least one cancellation path control signal to automatically adjust the cancellation path in real time, receive at least one demodulated signal, digitize the at least one demodulated signal, and update the at least one frequency control and cancellation path control signals.

Lux, James Paul↗

NASA NTRS2016

Maximum Likelihood Synchronization for Pulse Position Modulation with Inter-Symbol Guard Times

Deep space optical communications promises orders-of-magnitude growth in communication capacity, supporting high data rate applications such as video streaming and high-bandwidth science instruments. Pulse position modulation is the modulation format of choice for deep space applications, and by inserting inter-symbol guard times between the symbols, the signal carries the timing information needed by the demodulator. Accurately extracting this timing information is crucial to demodulating and decoding this signal. In this paper we propose a low complexity maximum likelihood timing estimator for pulse position modulation with inter-symbol guard times which significantly outperforms the prior art in this domain. We show that this estimator can achieve the same performance as prior estimators with an order-of-magnitude less signal flux, or multiple orders-of-magnitude less flux-accumulation time. Further we show that this estimator achieves the Cramer-Rao bound, making it asymptotically efficient. This method does not require an explicit synchronization sequence, freeing up channel resources for data transmission.

Rogalin, Ryan↗

NASA NTRS1964