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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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In this paper, we propose a novel method to design serial concatenation of an outer convolutional code with an inner trellis code with multi-level amplitude/phase modulations and a suitable bit-by-bit iterative decoding structure.
This paper describes the design of an ASIC performing the Viterbi decoder function with a constraint length of 15 and at a speed of 4.4 Mb/s. The architecture of the chip is described, as well as the design challenges which were overcome. The author also describes the successful application of the design system.
This paper describes the design of an ASIC performing the Viterbi decoder function with a constraint length of 15 and a speed of 4.4 Mb/s. The architecture of the chip is described, as well as the design challenges which were overcome. The author also describes the successful application of the design system.
This paper addresses the carrier-phase estimation problem under low SNR conditions as are typical of turbo- and LDPC-coded applications. In previous publications by the first author, closed-loop carrier synchronization schemes for error-correction coded BPSK and QPSK modulation were proposed that were based on feeding back hard data decisions at the input of the loop, the purpose being to remove the modulation prior to attempting to track the carrier phase as opposed to the more conventional decision-feedback schemes that incorporate such feedback inside the loop. In this paper, we consider an alternative approach wherein the extrinsic soft information from the iterative decoder of turbo or LDPC codes is instead used as the feedback.
In this paper, upper bounds to the average maximum-likelihood bit error probability of serially concatenated coding schemes are derived, design guidelines for the outer and inner codes that maximize the interleaver gain are presented, and finally, a highly-performing iterative decoding algorithm is proposed.
We propose a design approach for serial concatenation of an outer convolutional code and an inner trellis code with multilevel amplitude/phase modulations using a bit-by-bit iterative decoding scheme.
Error detection and correction system for decoding and evaluating redundant information contained in decimal time codes
Extension, modification and analysis of Gorenstein-Zierler decoding algorithm for binary codes of Bose, Ray-Chaudhuri and Hocquenghem /BCH/ correcting erasures and errors
Analog-to-digital coder and digital-to-analog decoder system handles wideband TV signals. The system incorporates solid state plug-in modular units and is operated in a VSD /Variable Slope Delta Modulation/ mode or in the conventional one-bit DM /Delta Modulation/ mode.
Encoding and decoding techniques using integrated circuits and applicable to binary digitizing of electrical analog information
Simplified, high-speed decoder of encoded binary data received over a noisy channel is provided in a versatile apparatus that can accommodate more than one particular set of codes. The apparatus is applicable to satellite, lunar, and planetary data transmission.
Performance evaluation of several convolutional and block codes with threshold decoding for space telemetry
Convolutional encoding-sequential decoding technique for coherent deep space telemetry link and near earth space missions
Decoder analysis for convolutional codes by stochastic sequential machine model
Feasibility and advantages of spacecraft fluidic decoder and display device
Simple decoding properties of Reed-Solomon codes for erasure channels combined with sequential coding for complex channels
Sequential decoder performance demonstration on data transmitted on spacecraft link, using Lunar Orbiter 5 and Deep Space Net Echo station
Markovian analysis of decoders for convolutional codes