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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Observing Quantum Measurement Collapse as a Learnability Phase Transition

During a quantum measurement, superpositions of states with different observable properties probabilistically collapse into one with a sharp value of the measured observable. In macroscopic quantum systems, this collapse arises via a continuous measurement-induced phase transition (MIPT) at a critical value of the strength of interaction with the measurement apparatus. MIPTs lie outside established paradigms for equilibrium or nonequilibrium critical phenomena and delineate distinct, stable dynamical and computational phases of matter. Quantum computers enable programmable simulation of the interaction of a measurement apparatus with a dynamical quantum system, to explore MIPT phenomena over a range of system sizes while retaining quantum coherence. Yet, existing experimental protocols rely on fundamentally nonscalable postselection techniques or direct classical simulation of quantum circuits. Here, we report the scalable observation of finite-size scaling evidence for an observable-sharpening MIPT in monitored quantum circuits in a chain of Yb + 171 ions in Quantinuum’s H1-1 trapped-ion quantum processor. By leveraging an equivalent description as a statistical physics problem, we implement scalable classical algorithms to infer the value of the measured observable from a single experimental shot. This technique enables a truly scalable protocol to observe observable-sharpening MIPTs in generic classes of circuits that cannot be directly classically simulated and also provides enhanced means to detect and suppress errors in the quantum simulation. Published by the American Physical Society 2024

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2026

Gaia: segmented germanium detector for high-energy X-ray fluorescence and spectroscopic imaging

We present Gaia, a monolithic array of 96 high-purity germanium pixel detectors integrated with a custom low-noise application-specific integrated circuit (ASIC) and a field-programmable gate array (FPGA)-based data acquisition system. The sensor operates at ∼100 K using a commercial closed-cycle cryocooler, with the in-vacuum electronics thermally isolated from the cold finger to ensure thermal stability. The system demonstrates an average energy resolution of 711 eV at 122 keV, measured using a 57 Co source, and 253 eV at 5.89 keV, measured with 55 Fe across all channels. The readout architecture incorporates a high-performance FPGA paired with a dual-core ARM processor, forming a complete embedded Linux-based computing platform. Communication between the processor and FPGA is handled via memory-mapped I/O, and data are streamed over high-speed gigabit Ethernet. A full-scale 384-pixel Gaia detector, based on this 96-element module, is currently under fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2025

A Novel Protection Scheme for Unbalanced Faults in Inverter Dominated Networks: A Computationally Efficient Algorithm for Entry-Level Relays

Microgrids are now a common practice in distribution systems to increase resilience and reliability. However, microgrid protection remains a critical challenge, considering its requirement to operate in both grid connected and islanded, and the variability in fault characteristics under each mode of operation. This paper presents unbalanced power (S unb ) based fault detection algorithm, which considers local voltage and current unbalances to determine faults in the system. S unb is a computationally efficient fault detection algorithm that is suitable for implementation in the programmable logic of entry level protective relays. In addition, the difference in current and voltage unbalance (D n ) is used to determine the fault type. The proposed method demonstrates high sensitivity and selectivity for line-to-ground (LG), line-to-line (LL), and double line-to-ground (LLG) faults, representing the most common faults in distribution systems. It also allows relay coordination with upstream and downstream protection devices in both island and grid connected operation, while preserving grading margins. The same pickup and time multiplier settings of a particular relay for both modes of operation eliminates the need for adaptive settings, which rely on communication networks. Validation was performed with a hardware-in-the-loop (HIL) setup using Typhoon HIL real time simulator interfaced with three entry-level, SEL 751 relays. Results confirmed the algorithm’s ability to discriminate fault conditions, and determine the fault type under both operating modes, maintain fast detection times, and ensure proper protection coordination.

fault classification↗
DOE OSTI2026

A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques

Processing-in-Memory (PIM) is emerging as a practical path to overcome the limitations of traditional von Neumann architectures. At its core, PIM systems implement computing primitives such as logic operations and multiply-accumulate acceleration through compute-in-memory, near-memory processing, or hybrid designs. The role of memory cells varies widely across technologies, acting as inputs, outputs, or analog accumulators through bit-lines and sense amplifiers. This diversity creates trade-offs in precision, bandwidth, latency, and programmability, making it difficult to build a unified understanding on the progress of the field. In this survey, we organize recent advances of PIM into three areas. First, we discuss the progress on the architectural optimizations of PIM and its integration with both DRAM and emerging non-volatile memories. Second, we examine how PIM is being used to accelerate key computing domains, including generative AI workloads and high-performance kernels, along with new approaches. Third, we highlight the growing adoption of PIM in computational sciences, where it is being applied to solve interdisciplinary problems such as genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation. Finally, we synthesize the major challenges that continue to slow PIM adoption, including manufacturing constraints, power delivery, thermal reliability, data consistency, runtime and memory-management coordination, and the difficulty of building portable software abstractions without sacrificing commercial viability. This work provides an updated, structured perspective on PIM’s potential across computing and computational sciences and the barriers that must be solved for it to reach its full impact.

Asifuzzaman, Kazi [Oak Ridge National Laboratory (↗
DOE OSTI2024

FTTN: Feature-Targeted Testing for Numerical Properties of NVIDIA & AMD Matrix Accelerators

While NVIDIA has been the dominant provider of GPUs for HPC and ML, now AMD has several offerings of GPUs. This encourages programmers to try out AMD GPUs for new codes and also port existing codes over. Unfortunately, without understanding the floating-point differences between these GPU types, software development or porting can introduce bugs—and currently such an understanding is lacking. The magnitude of this open question becomes clear if one imagines the the number of floating-point precision choices (FP16, FP32, etc.), floating-point formats (standard floats, brain-float, etc.), and execution units available (elementary units, matrix/tensor cores, etc.) Questions such as rounding modes and subnormal support are also important. Most of these answers are unknown today or are hard to access. We provide the first testing-guided approach that answers a significant number of these questions. We also devise tests to reveal internal information (e.g., extra bits kept) to make sure that our findings are reliable. Many of our tests employ systematically generated random-programs, others apply fast-math flags and some involve fused multiplyadd. Especially for tensor/matrix cores, the tests have nontrivial logic that we present Our testing approach is reusable for the plethora of GPUs yet to be introduced. Our findings include up to 7 ulps of difference between NVIDIA and AMD for sin and cos at FP32 precision and 3 ulp at FP64. In our study of matrix cores (NVIDIA) and tensor cores (AMD), we have extensively characterized rounding modes (truncation versus round-to-nearest), the number of extra internal bits kept (whether 3 bits are kept or not), subnormal support for inputs and outputs across four different floating-point formats and across NVIDIA A100 and AMD MI250X GPUs. We believe that this wealth of data becoming available for the first time may help avoid significant porting bugs when migrating code across these platforms.

Li, Xinyi↗
DOE OSTI2024

CHARM-SYCL & IRIS: A Tool Chain for Performance Portability on Extremely Heterogeneous Systems

Performance portability is becoming crucial as high-performance computing systems become increasingly heterogeneous. We have many options for CPUs and accelerators (e.g., GPUs) but also for non-Von Neumann architectures such as field-programmable gate arrays. This paper presents the CHARM-SYCL unified programming environment for multiple accelerator types as a performance-portable programming environment. It uses the IRIS library developed at Oak Ridge National Laboratory as the back end accelerator runtime. IRIS has a high-performance scheduler to distribute tasks across accelerators. This design allows us to run an application from the same source on multiple systems with multiple configurations. We provide three types of portability with CHARM-SYCL: Portable Workflow, Compiler and Runtime Portability, and Application and Performance Portability. We implement a Monte Carlo simulation benchmark code on the CHARM-SYCL execution environment and demonstrate that our programming environment can accommodate extremely heterogeneous systems.

Fujita, Norihisa↗
DOE OSTI2025

Enabling Scientific Applications with Performance-Portability and High-Productivity for Multi-GPU Programming with JACC.Multi

This work bridges the gap between multi-GPU computing and high-productivity, performance-portable programming solutions. Our goal is to enhance scientific applications with a productive and portable solution—program once, deploy everywhere—for multi-GPU programming with no cost to programmability. To accomplish this, we implemented JACC.Multi, which is part of the Julia for ACCelerators (JACC) performance-portable framework. JACC. Multi is the only high-level, portable metaprogramming solution that targets multi-GPU environments and is integrated in a readily accessible programming language (e.g., Julia language). With transparent GPU-to-GPU communication, JACC. Multi is optimized for scientific application workloads and is portable for NVIDIA and AMD accelerators. For the evaluation, we use two modern multi-GPU systems: Hudson, which features two NVIDIA H100 Hopper GPUs per node, and Frontier, which features four AMD MI250X GPUs per node, each with two Graphics Compute Dies (GCDs) for a total of eight GCDs per node. Additionally, as part of the evaluation, we use JACC (one GPU), MPI+JACC, and JACC. Multi codes that implement well-known and widely used scientific algorithms/kernels such as the conjugate gradient algorithm and an explicit forward Euler solver that requires GPU-to-GPU communication. Overall, JACC. Multi codes achieve better performance than MPI+JACC codes and significant speedups over JACC (one GPU), with up to 1.9× on Hudson and 6× on Frontier.

Valero Lara, Pedro [ORNL] (ORCID:0000000214794310)↗
DOE OSTI2025

Flexible Operation of Microgrids Through Operator-Configurable Microgrid Controllers

Microgrids are becoming critical assets in power distribution systems. This is partly due to the resiliency and reliability challenges faced by power distribution systems in the last decade and partly due to the increased integration of distributed energy resource assets, such as solar photovoltaic. This increased need for microgrids has created a multitude of needs for microgrid controllers. Most microgrid controllers in the past decade have been uniquely programmed or custom programmed to meet the needs of a specific microgrid. Currently, IEEE standards aim to integrate the needs and capabilities of microgrid controllers under a unified umbrella. But the standards do not recommend necessary or appropriate software development practices for microgrid controllers. In addition, the programmable nature and maintenance of controllers are also key characteristics that fall outside the coverage of the standards. In this paper, we present the best software practices that utility engineers and microgrid operators should consider in the microgrid software platform. This paper can be used as an information document for developing documentation of controller requirements and assessing microgrid controller requirements.

Banshee microgrid↗
DOE OSTI2024

Neuro-Spark: A Submicrosecond Spiking Neural Networks Architecture for In-Sensor Filtering

Neuro-Spark, which is a new neuromorphic architecture with a field-programmable gate array (FPGA) implementation for ultrafast spiking neural network (SNN) inference at the edge, facilitates smart-pixel in-sensor filtering for high-energy physics experiments at the Large Hadron Collider (LHC). Utilizing the evolutionary optimization for neuromorphic systems (EONS) training method, we generate compact SNN models with 91% signal efficiency, akin to convolutional neural networks but with half the parameters. However, deploying near the detector poses a challenge because the SNN must handle a sustained input data rate exceeding 1013 GB/s. To overcome this, we propose a novel hardware architecture that uses high-level synthesis to construct a tuned architecture for the EONS-trained SNN. In addition to the analysis and validation with an AMD Xilinx Artix-A7 FPGA, our solution consumes only ç24% of FPGA LUT and flipflops. We also introduce an innovative quantization method that reduces FPGA resource utilization by ç15% without compromising accuracy. Our FPGA implementation achieves computing latency of ç10 ns for smart-pixel application inference on an edge FPGA.

Miniskar, Narasinga Rao↗
DOE OSTI2024

Disruption of Commercial Solar Inverter System by TLS Proxy Man-in-the-Middle Attack

Transport Layer Security (TLS) is a cryptographic protocol that encrypts communication data, providing end-to-end communication encryption and authentication. Currently, TLS is widely adopted for securing communication between servers and end devices, including solar inverter systems. Therefore, users/operators can securely access the solar inverters through a web user interface (WebUI) application programmable interface (API) on a PC or server over TLS-enabled Wi-Fi or Ethernet. However, the security of the TLS-based network becomes compromised if it is breached by a TLS proxy man-in-the-middle (MITM) exploit. This report explores potential vulnerabilities in a commercial solar inverter system that leverages a TLS proxy MITM and discusses the impacts through assume-breached penetration testing. Furthermore, the paper explores recommended mitigation methods against the TLS proxy MITM exploit in solar inverters.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Mission planning for photogrammetry-based autonomous 3D Mapping of Dams using a commercial UAV

The application of autonomous unmanned aerial vehicles (UAVs) for conducting inspections of dams represents an innovative approach aimed at enhancing safety, efficiency, and cost-effectiveness. In this context, this paper presents algorithms for UAV mission design in autonomous dam inspections that include the creation of a 3D map based on photogrammetry. The algorithms were systematically developed to incorporate a comprehensive set of parameters that account for the geometric characteristics of the dam and adhere to photogrammetry specifications. To validate the proposed methodology, we utilized a commercial programmable quadrotor, specifically the Parrot Anafi USA Gov drone, which is equipped with high-quality cameras and can be programmed with the help of a software development kit (SDK) provided by the manufacturer. Our results demonstrate the efficacy of our method, highlighting how the generated maps can be used for hazard detection in the downstream slope of dams.

42 ENGINEERING↗
DOE OSTI2025

Implementing Directive-Based Deferred Execution for Effective Network Aggregation

Remote direct memory access technology provides an efficient mechanism for one-sided communication that can be leveraged to implement a distributed shared memory programming model. However, when applications generate large numbers of small, irregular messages, network congestion often arises. Existing solutions address this small message problem by facilitating message aggregation but typically require disruptive code transformations that detract from the algorithmic intent of applications, or can be limited by dependent operations on aggregated data between synchronisation points. A solution is to use a directive-assisted approach that enables compilers to transform code dependent on aggregated communication for deferred execution. This paper presents an algorithm that a compiler can use to implement and optimise deferred execution for code dependent on aggregated data, based on an "aggregation context" extension for the OpenSHMEM partitioned global address space library. This new capability addresses a key challenge of message aggregation, allowing its full potential to reduce network congestion and enhance programmability to be realised.

Welch, Aaron [ORNL]↗
DOE OSTI2025

A Digital Three Level Space Vector Modulator for High Frequency Vector Sequence Generation

This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.

active neutral point clamped inverter↗
DOE OSTI2025

A High-Current Pulsed Prototype Power Supply

The Accelerator Controls Operations Research Network (ACORN) project aims to modernize the accelerator control system and replace aging power supplies at Fermilab. As part of this effort, outdated RF ferrite bias power supplies will be redesigned. These power supplies are essential for tuning the resonant frequency of RF cavities by delivering programmable current outputs of up to 2500 A and voltages ranging from −10 V to +35 V. They operate at a repetition rate of 15 Hz in the Booster ring, and 1 Hz at the Main Injector ring. The power supplies utilize a bank of transistors in the linear region, connected in parallel with the load, to actively regulate the output current from a 12-pulse SCR bridge. To support this upgrade, a new bias power supply topology was developed as proof of concept. The design utilizes an IGBT Hbridge operating in Pulse Width Modulation (PWM) mode, controlled by a microcontroller. A prototype, constructed using spare components, successfully delivered an output current of 500 A at a repetition rate of 15 Hz during initial testing. The circuit's bandwidth was measured at 480 Hz, highlighting opportunities for further optimization in the controller design to achieve the target bandwidth of 2 kHz.

Bullman, Austin [ORNL]↗
DOE OSTI2024

AutoCheck: Automatically Identifying Variables for Checkpointing by Data Dependency Analysis

Checkpoint/Restart (C/R) has been widely deployed in numerous HPC systems, Clouds, and industrial data centers, which are typically operated by system engineers. Nevertheless, there is no existing approach that helps system engineers without domain expertise and domain scientists without system fault tolerance knowledge identify those critical variables accounted for correct application execution restoration in a failure for C/R. To address this problem, we propose an analytical model and a tool (AutoCheck) that can automatically identify critical variables to checkpoint for C/R. AutoCheck relies on first, analytically tracking and optimizing data dependency between variables and other application execution state, and second, a set of heuristics that identify critical variables for checkpointing from the refined data dependency graph (DDG). AutoCheck allows programmers to pinpoint critical variables to checkpoint quickly within a few minutes. We evaluate AutoCheck on 13 representative HPC benchmarks, demonstrating that AutoCheck can efficiently identify correct critical variables to checkpoint.

HPC↗
DOE OSTI2024

Object Proxy Patterns for Accelerating Distributed Applications

Workflow and serverless frameworks have empowered new approaches to distributed application design by abstracting compute resources. However, their typically limited or one-size-fits-all support for advanced data flow patterns leaves optimization to the application programmer—optimization that becomes more difficult as data become larger. The transparent object proxy, which provides wide-area references that can resolve to data regardless of location, has been demonstrated as an effective low-level building block in such situations. Here we propose three high-level proxy-based programming patterns—distributed futures, streaming, and ownership—that make the power of the proxy pattern usable for more complex and dynamic distributed program structures. We motivate these patterns via careful review of application requirements and describe implementations of each pattern. As a result, we evaluate our implementations through a suite of benchmarks and by applying them in three meaningful scientific applications, in which we demonstrate substantial improvements in runtime, throughput, and memory usage.

Distributed Computing↗
DOE OSTI2024

Numerical Simulation of Irradiation Induced Swelling for STAR 4.1 Blanket

Here, this article presents the preliminary results of FEM implementation of irradiation-induced swelling, hardening, and creep effect using ANSYS user programmable features (UPFs) applied to material properties. The first liquid metal breeding blanket model for STAR 4.1 tokamak as a part of the virtual prototyping system is under development at Princeton Plasma Physics Laboratory (PPPL). Intense neutron irradiation produces significant changes in the physical and mechanical properties of Fe-(8%–9%)Cr-based reduced activation ferritic martensitic (RAFM) steels. An ANSYS model of the breeding blanket was built to involve these irradiation-induced material property changes with neutron fluence distribution mapped from the MCNP model. Simulation results show that significant structure deformation forms from nuclear swelling, stress, and plastic strain arising from DPA gradient through wall thickness. The material degradation effect is not negligible. This modeling feature can either assist in analyzing the structural behaviors with the influence of nuclear swelling or provide guidance to design the structure to withstand irradiation.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

Real-Time Ethernet Interface for NSTX-U’s Thomson Scattering Diagnostic (2023)

Here, the multipoint Thomson scattering (MPTS) diagnostic system at the National Spherical Torus Experiment Upgrade (NSTX-U) facility is undergoing an upgrade to operate in real-time and interface with the plasma control system (PCS) for NSTX-U. Previous prototyping efforts have shown that spectral analysis and rapid calculations of electron temperature and density are possible on a real-time Linux machine when using up to a 100-Hz laser pulse repetition rate. A remaining challenge was transferring the real-time data to NSTX-U’s PCS, which utilizes the front panel data port (FPDP) protocol. The original proposed method was to convert the real-time data into analog values, but a new solution was developed to keep the output format digital by using an Ethernet controller with a field-programmable gate array (FPGA). This article focuses on a new input module that has been developed to accept incoming user datagram protocol (UDP) packets sent over Ethernet, convert into FPDP format, and integrate into the existing data stream under NSTX-U’s real-time framework.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗