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At least 253 records · Page 14

Phase identification using statistical analysis

A device includes at least one processor configured to determine, based on (i) a first plurality of time-varying electrical measurements corresponding to a feeder head of a power distribution network having a plurality of phases and (ii) a second plurality of time-varying electrical measurements corresponding to a node in the power distribution network, and using statistical analysis, a predicted phase, from the plurality of phases, that corresponds to the node. The processor may be configured to use ranked correlation coefficients (such as the Kendall rank correlation coefficient) to determine the predicted phase and may use principle component analysis. The processor is also configured to cause at least one device of the power distribution network to modify operation based at least on part on the predicted phase.

Veda, Santosh Sambamoorthy↗

Systems and methods for tensor scheduling

A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.

Meister, Benoit J.↗

In situ data acquisition and real-time analysis system

A testing system for evaluating the performance of an electrical/electronic UUT under dynamic operating conditions. The testing system includes a dynamic testing component (e.g., a centrifuge) for applying a stimulus to the UUT, and an iDAQ system configured to perform in situ data acquisition and real-time data analysis. The iDAQ system may also be subject to the stimulus. The iDAQ system includes a processor (e.g., an SoC) component, a power supply, a CR/I component, an IR component, and a single enclosure. The processor component may control the dynamic testing component, including varying in real-time the stimulus applied to the UUT. The processor component may include multiple input channels, and a high current/voltage subcomponent of the power supply may be configured to supply up to five hundred volts.

Benyhesan, Mohammad K.↗

Cooperative workgroup scheduling and context prefetching based on predicted modification of signal values

A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to preempting the first workgroup and in response to the signal having a second value. A third context it is prefetched into registers of the processor core based on the first hint and the second value. The first context is stored in a first portion of the registers and the second context is prefetched into a second portion of the registers prior to preempting the first workgroup.

Dutu, Alexandru↗

Event detection unit

An event detection unit (EDU) for detecting an explosive event is provided. The EDU includes different types of sensors for measuring characteristics of an explosive event. The EDU includes an event notification component. The EDU also includes a processor that receives a measurement from the sensors and generates a combined non-event probability and a combined event probability based on that measurement that indicates a likelihood that an explosive event has not occurred or has occurred. The processor determines whether an explosive event has occurred based on the non-event probabilities and event probabilities. When an explosive event has been determined to occur, the processor directs the event notification component to output a notification that an explosive event has occurred.

Candy, James Vincent↗

Hardware accelerated dynamic work creation on a graphics processing unit

A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Gutierrez, Anthony T.↗

Three-dimensional broadband nonlinear phased array imaging

System include an ultrasonic transducer configured to couple to a nondestructive testing (NDT) sample and configured to produce and direct an ultrasonic probe wave at a selected frequency into a subsurface region of the NDT sample, a 3D laser scanning vibrometer configured to direct a detection beam in a scan area on a surface of the NDT sample and to receive a return beam from the scan area, and to detect, based on the return beam, a 3D motion of the surface across a wideband frequency range, and a processor, and a memory configured with instructions that, when executed by the processor, cause the processor to produce sub-surface image data of the NDT sample at multiple harmonics of the selected frequency in the wideband frequency range based on the detected 3D surface motion, wherein the sub-surface image data describes a nonlinear defect response produced in the NDT sample by interaction of the ultrasonic probe wave with the subsurface region.

Remillieux, Marcel↗

Real time feedback-based optimization of distributed energy resources

An example device includes a processor configured to receive a plurality of voltage values representing respective voltage magnitudes at voltage nodes in a first portion of a power system and determine, for each voltage node, a respective value of first and second voltage-constraint coefficients. The processor is also configured to receive a power value corresponding to a connection point of the first portion of the power system with a second portion of the power system and determine for the connection point, a respective value of first and second power-constraint coefficients. The processor is also configured to cause at least one energy resource connected to the first portion of the power system to modify an output power of the at least one energy resource based on the value of the first and second voltage-constraint coefficients for each voltage node and the value of the first and second power-constraint coefficients.

Dall'Anese, Emiliano↗

Accelerated pattern matching method on a quantum computing system

A method of determining a pattern in a sequence of bits using a quantum computing system includes setting a first register of a quantum processor in a superposition of a plurality of string index states, encoding a bit string in a second register of the quantum processor, encoding a bit pattern in a third register of the quantum processor, circularly shifting qubits of the second register conditioned on the first register, amplifying an amplitude of a state combined with the first register in which the circularly shifted qubits of the second register matches qubits of the third register, measuring an amplitude of the first register and determining a string index state of the plurality of string index states associated with the amplified state, and outputting, by use of a classical computer, a string index associated with the first register in the measured state.

NIROULA, Pradeep↗

Panel Session 70: Nuclear Power Plant Waste Management, LLRW Processing Issues

This panel focused on senior utility managers discussing issues with commercial LLW processors. LLW processors had an opportunity to update utilities/NPPs on new or different services or technologies being offered to assist in their radioactive waste management goals, changes to their facility license, revisions to their acceptance guidelines, and emerging compliance issues. Panelists with presentations: UniTech - 'Expanding to Reduce Costs' LLW Processor Update (Gregg Johnstone); Veolia Nuclear Solutions Federal Services - Alaron Nuclear Services (Dave Garber); EnergySolutions Tennessee Processing Facilities (Fred Schulz); Complex Waste Management Issues Services and Treatment Facilities (George M. Taylor)

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗

Event detection unit

An event detection unit (EDU) for detecting an explosive event is provided. The EDU includes different types of sensors for measuring characteristics of an explosive event. The EDU includes an event notification component. The EDU also includes a processor that receives a measurement from the sensors and generates a combined non-event probability and a combined event probability based on that measurement that indicates a likelihood that an explosive event has not occurred or has occurred. The processor determines whether an explosive event has occurred based on the non-event probabilities and event probabilities. When an explosive event has been determined to occur, the processor directs the event notification component to output a notification that an explosive event has occurred.

Candy, James Vincent↗

Ripple-type control of networked physical systems

Techniques for ripple-type control of networked physical systems such as power systems, water systems, and others are provided. As one example, a device includes at least one processor configured to determine, for a first controllable device in a system, based on a measurement of an output parameter and a minimum output parameter value, an output violation value for the first device. The processor is further configured to determine, based on a present input value for the first device, the output violation value, and an assistance requisition value corresponding to a second device, a target input value for the first device. The processor is further configured to cause the first controllable device to modify operation based on the target input value and a maximum input value for the first controllable device.

Cavraro, Guido↗

Systems and methods for predictive lane change

A system includes a controller comprising at least one processor coupled to a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform operations comprising: receiving information indicative of operation of the vehicle and of a driving condition for the vehicle; determining that a speed of the vehicle is less than a target speed for the vehicle based on the received information; determining, in response to the determination that the speed is less than the target speed, that the lane change and takeover event is at least one of feasible or efficient based on the received information; and providing, in response to the determination regarding the lane change and takeover event, a notification.

Borhan, Hoseinali↗

Andes Data Analysis System at the Oak Ridge Leadership Computing Facility

Andes is a (704)-node commodity-type Linux® cluster. Each of Andes’s 704 nodes contain two 16-core 3.0 GHz AMD EPYC 7302 processors with AMD’s Simultaneous Multithreading (SMT) Technology and 256GB of main memory. Andes also has nine large memory GPU nodes. These nodes each have 1TB of main memory and two NVIDIA K80 GPUs with two 14-core 2.30 GHz Intel Xeon processors with HT Technology.

AMD EPYC↗

Identification of Defects and the Origins of Surface Noise on Hydrogen–Terminated (100) Diamond

Near-surface nitrogen vacancy centres are critical to many diamond-based quantum technologies such as information processors and nanosensors. Surface defects play an important role in the design and performance of these devices. The targeted creation of defects is central to proposed bottom-up approaches to nanofabrication of quantum diamond processors, and uncontrolled surface defects may generate noise and charge trapping which degrade shallow NV device performance. Surface preparation protocols may be able to control the production of desired defects and eliminate unwanted defects, but only if their atomic structure can first be conclusively identified. This work uses a combination of scanning tunnelling microscopy (STM) imaging and first-principles simulations to identify several surface defects on H:C(100)—2 × 1 surfaces prepared using chemical vapour deposition (CVD). The atomic structure of these defects is elucidated, from which the microscopic origins of magnetic noise and charge trapping are determined based on the modeling of their paramagnetic properties and acceptor states. Rudimentary control of these deleterious properties is demonstrated through STM tip-induced manipulation of the defect structure. Furthermore, the results validate accepted models for CVD diamond growth by identifying key adsorbates responsible for the nucleation of new layers.

36 MATERIALS SCIENCE↗

HIPLZ: Enabling performance portability for exascale systems

While heterogeneous computing has emerged as a dominant trend in current and future High-Performance Computing (HPC) systems, it is also widely recognized that this shift has led to increased software complexity due to a proliferation of programming systems for different heterogeneous processors. One such example is the Heterogeneous-Compute Interface for Portability from AMD (HIP ), which is composed of a C Runtime API and C++ Kernel Language. Many HPC applications will likely use HIP on future exascale systems (e.g., Frontier and El Capitan), but HIP currently only targets AMD and NVIDIA processors. This limitation creates challenges for users who would also like to run their applications on exascale systems based on other architectures (e.g., Aurora, which is based on Intel hardware) that are currently not targeted by HIP . In this paper, we introduce the design and implementation of HIPLZ , a compiler and runtime system that uses the Intel Level Zero API to support HIP on Intel GPU architectures. We discuss the design of HIPLZ , derived from HIPCL (an implementation of HIP on top of OpenCL ), and portability issues that occur from using the Level Zero runtime as a backend. We evaluate our implementation by running several performance benchmarks and mini-apps written in HIP on Intel architectures using HIPLZ . Our results show that this approach provides competitive performance relative to Intel's OpenCL implementations on Intel Gen9 and UHD Graphics 770 GPUs, while providing good coverage of features needed by HPC applications. Overall, this approach is a promising demonstration of enabling performance portability for exascale systems.

97 MATHEMATICS AND COMPUTING↗

Multilevel Graph Partitioning for Three-Dimensional Discrete Fracture Network Flow Simulations

We present a topology-based method for mesh-partitioning in three-dimensional discrete fracture network (DFN) simulations that takes advantage of the intrinsic multi-level nature of a DFN. DFN models are used to simulate flow and transport through low-permeability fractured media in the subsurface by explicitly representing fractures as discrete entities. The governing equations for flow and transport are numerically integrated on computational meshes generated on the interconnected fracture networks. Modern high-fidelity DFN simulations require high-performance computing on multiple processors where performance and scalability depends partially on obtaining a high-quality partition of the mesh to balance work-loads and minimize communication across all processors. The discrete structure of a DFN naturally lends itself to various graph representations, which can be thought of as coarse-scale representations of the computational mesh. Using this concept, we develop two applications of the multilevel graph partitioning algorithm to partition the mesh of a DFN. In the first, we project a partition of the graph based on the DFN topology onto the mesh of the DFN and in the second, this DFN-based projection is used as the initial condition for further partitioning refinement of the mesh. We compare the performance of these methods with standard multi-level graph partitioning using graph-based metrics (cut, imbalance, partitioning time), computational-based metrics (FLOPS, iterations, solver time), and total run time. The DFN-based and the mesh-based partitioning methods are comparable in terms of the graph-based metrics, but the time required to obtain the partition is several orders of magnitude faster using the DFN-based partitions. The computation-based metrics show comparable performance between both methods so, in combination, the DFN-based partitions are several orders of magnitude faster than the mesh-based partition. Furthermore, the method which uses the DFN-partition solution as the initial condition of the mesh partition provided cut and imbalance values that were close to the mesh-based partition but in a fraction of the time. In turn, this hybrid method outperformed both of the other methods in terms of the total run time.

58 GEOSCIENCES↗

Quantum Divide and Compute: Exploring the Effect of Different Noise Sources

Abstract Our recent work (Ayral et al. in Proceedings of IEEE computer society annual symposium on VLSI, ISVLSI, pp 138–140, 2020. 10.1109/ISVLSI49217.2020.00034 ) showed the first implementation of the Quantum Divide and Compute (QDC) method, which allows to break quantum circuits into smaller fragments with fewer qubits and shallower depth. This accommodates the limited number of qubits and short coherence times of quantum processors. This article investigates the impact of different noise sources—readout error, gate error and decoherence—on the success probability of the QDC procedure. We perform detailed noise modeling on the Atos Quantum Learning Machine, allowing us to understand tradeoffs and formulate recommendations about which hardware noise sources should be preferentially optimized. We also describe in detail the noise models we used to reproduce experimental runs on IBM’s Johannesburg processor. This article also includes a detailed derivation of the equations used in the QDC procedure to compute the output distribution of the original quantum circuit from the output distribution of its fragments. Finally, we analyze the computational complexity of the QDC method for the circuit under study via tensor-network considerations, and elaborate on the relation the QDC method with tensor-network simulation methods.

97 MATHEMATICS AND COMPUTING↗