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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

Silicon device performance measurements to support temperature range enhancement

Testing of the metal oxide semiconductor (MOS)-controlled thyristor (MCT) has uncovered a failure mechanism at elevated temperature. The failure appears to be due to breakdown of the gate oxide. Further testing is underway to verify the failure mode. Higher current level inverters were built to demonstrate 200 C operation of the N-MOSFET's and insulated-gate-bipolar transistors (IGBT's) and for life testing. One MOSFET failed early in testing. The origin of this failure is being studied. No IGBT's have failed. A prototype 28-to-42 V converter was built and is being tested at room temperature. The control loop is being finalized. Temperature stable, high value (10 micro-F) capacitors appear to be the limiting factor in the design at this time. In this application, the efficiency will be lower for the IGBT version due to the large V sub(cesat) (3.5-4 V) compared to the input voltage of 28 V. The MOSFET version should have higher efficiency; however, the MOSFET does not appear to be as robust at 200 C. Both versions are built for comparison.

Bromstead, James↗
NASA NTRS2010

N channel JFET based digital logic gate structure

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Krasowski, Michael J.↗
NASA NTRS1972

Temperature compensation of light emitting diodes and photodiodes.

Improved temperature compensation of the output from a GaAs LED can be obtained by connecting the diode in series with the emitter of an n-p-n transistor whose base circuit incorporates a high-gain operational amplifier and a parallel thermistor-resistor network. The temperature dependence of several photodiodes is also reported along with a practical temperature compensation scheme. Finally, the temperature compensation of a photon coupled pair consisting of a GaAs LED and a silicon photodiode is described. The combination provides a stability, linearity, and repeatability of about 1% over the upper 60% of the LED forward current range in the temperature interval from 15 to 45 C.

Burrous, C. N.↗
NASA NTRS1972

Hardening electronic devices against very high total dose radiation environments

The possibilities and limitations of hardening silicon semiconductor devices to the high neutron and gamma radiation levels and greater than 10 to the eighth power rads required for the NERVA nuclear engine development are discussed. A comparison is made of the high dose neutron and gamma hardening potential of bipolar, metal insulator semiconductors and junction field effect transistors. Experimental data is presented on device degradation for the high neutron and gamma doses. Previous data and comparisons indicate that the JFET is much more immune to the combined neutron displacement and gamma ionizing effects than other transistor types. Experimental evidence is also presented which indicates that p channel MOS devices may be able to meet the requirements.

Buchanan, B.↗
NASA NTRS2002

Electrical Characterization of Polyaniline/polyethylene Oxide Nanofibers for Field Effect Transistors

Nanofibers comprised of polyaniline/polyethylene oxide (PANI/PEO) are being developed for novel logic devices. We report the electrical conductivity of PANI/PEO nanofibers with diameters in the 100 to 200 nm range. We measured conductivity values of approx. 0.3 to 1.0 S/cm, which is higher than the values reported for thicker nanofibers, but less than the bulk value of PANI. The electrical measurements were performed by depositing the fibers on pre-electroded, oxidized silicon (Si) substrates. The excellent adherence of the nanofibers to the SiO2 as well as the gold (Au) electrodes may be useful in the design of future devices.

Mueller, Carl H.↗
NASA NTRS1985

Experimental study of the minority-carrier transport at the polysilicon-monosilicon interface

This paper presents the results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contacts. Polysilicon contacts were deposited and heat treated at different conditions. The electrical properties were measured using p-n junction test structures that are much more sensitive to the contact properties than are bipolar transistors. A simple phenomenological model was used to correlate the structural properties with electrical measurements. Possible transport mechanisms are examined and estimates are made about upper bounds on transport parameters in the principal regions of the devices. The main conclusion of this study is that the minority-carrier transport in the polycrystalline silicon is dominated by a highly disordered layer at the polysilicon-monosilicon interface characterized by very low minority-carrier mobility. The effective recombination velocity at the n(+) polysilicon-n(+) monosilicon interface was found to be a strong function of fabrication conditions. The results indicate that the recombination velocity can be much smaller than 10,000 cm/s.

Neugroschel, A.↗
NASA NTRS1979

Heavily doped transparent-emitter regions in junction solar cells, diodes, and transistors

The paper presents an analytical treatment of transparent-emitter devices, particularly solar cells, that is more complete than previously available treatments. The proposed approach includes the effects of bandgap narrowing, Fermi-Dirac statistics, built-in field due to impurity profile, and a finite surface recombination velocity at the emitter surface. It is demonstrated that the transparent-emitter model can predict experimental values of Voc observed on n(plus)-p thin diffused junction silicon solar cells made on low-resistivity (0.1 ohm-cm) substrates. A test is included for the self-consistent validity of the transparent-emitter model. This test compares the calculated transit time of minority carriers across the emitter with the Auger-impact minority-carrier lifetime within the emitter region.

Shibib, M. A.↗
NASA NTRS1979

Development of non-volatile semiconductor memory

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Heikkila, W. W.↗
NASA NTRS2007

An Overview of Wide Bandgap Silicon Carbide Sensors and Electronics Development at NASA Glenn Research Center

A brief overview is presented of the sensors and electronics development work ongoing at NASA Glenn Research Center which is intended to meet the needs of future aerospace applications. Three major technology areas are discussed: 1) high temperature SiC electronics, 2) SiC gas sensor technology development, and 3) packaging of harsh environment devices. Highlights of this work include world-record operation of SiC electronic devices including 500?C JFET transistor operation with excellent properties, atomically flat SiC gas sensors integrated with an on-chip temperature detector/heater, and operation of a packaged AC amplifier. A description of the state-of-the-art is given for each topic. It is concluded that significant progress has been made and that given recent advancements the development of high temperature smart sensors is envisioned.

Hunter, Gary W.↗
NASA NTRS1999

Silicon Carbide Being Developed for High-Definition Television (HDTV) Transmitter Modules

Through a Space Act Agreement, the NASA Lewis Research Center has helped develop the base silicon carbide (SiC) epitaxial growth technology for Westinghouse's efforts to bring silicon carbide products to the marketplace. SiC is a high-temperature, high-voltage semiconductor that can deliver greater than three times the power of conventional silicon devices. The technology was initially disclosed in the 1994 R&T report. NASA Lewis High Temperature Integrated Electronics and Sensors (HTIES) team is developing SiC as a material for advanced semiconductor electronic device applications because SiC-based electronics and sensors can operate in hostile environments where conventional silicon-based electronics cannot function. SiC transmitters hold great promise for television stations because they can convert broadcasts from analog to digital signals. A modular solid-state design provides broadcasters with an option to gradually add modules, increasing the power of their transmitters as they expand their high-definition television (HDTV) coverage. Using these high-power transistors will significantly reduce the space needed for high-power transmitters at television stations and will offer a solid-state solution, reducing long-term maintenance costs. Thus, transmitter manufacturers will be able to abandon their reliance on tube-based technology for high-power transmitters and will be able to build smaller, high-power, solid-state transmitters.

Costello, Donald E.↗
NASA NTRS2011

Improving Single Event Effects Testing Through Software

Radiation encountered in space environments can be damaging to microelectronics and potentially cause spacecraft failure. Single event effects (SEE) are a type of radiation effect that occur when an ion strikes a device. Single event gate rupture (SEGR) is a type of SEE that can cause failure in power transistors. Unlike other SEE rates in which a constant linear energy transfer (LET) can be used, SEGR rates sometimes require a non-uniform LET to be used to be accurate. A recent analysis shows that SEGR rates are most easily calculated when the environment is described as a stopping rate per unit volume for each ion species. Stopping rates in silicon for pertinent ions were calculated using the Stopping and Range of Ions in Matter (SRIM) software and CREME-MC software. A reference table was generated and can be used by others to calculate SEGR rates for a candidate device. Additionally, lasers can be used to simulate SEEs, providing more control and information at lower cost than heavy ion testing. The electron/hole pair generation rate from a laser pulse in a semiconductor can be related to the LET of an ion. MATLAB was used to generate a plot to easily make this comparison.

generation equation↗
NASA NTRS2015

Performance Evaluation of an Automotive-Grade, High Speed Gate Driver for SiC FETs, Type UCC27531, Over a Wide Temperature Range

Silicon carbide (SiC) devices are becoming widely used in electronic power circuits as replacement for conventional silicon parts due to their attractive properties that include low on-state resistance, high temperature tolerance, and high frequency operation. These attributes have a significant impact by reducing system weight, saving board space, and conserving power. In this work, the performance of an automotive-grade high speed gate driver with potential use in controlling SiC FETs (field-Effect Transistors) in converters or motor control applications was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Transistor Gate Drive↗
NASA NTRS2006

FETs Based on Doped Polyaniline/Polyethylene Oxide Fibers

A family of experimental highly miniaturized field-effect transistors (FETs) is based on exploitation of the electrical properties of nanofibers of polyaniline/ polyethylene oxide (PANi/PEO) doped with camphorsulfonic acid. These polymer-based FETs have the potential for becoming building blocks of relatively inexpensive, low-voltage, highspeed logic circuits that could supplant complementary metal oxide/semiconductor (CMOS) logic circuits. The development of these polymerbased FETs offers advantages over the competing development of FETs based on carbon nanotubes. Whereas it is difficult to control the molecular structures and, hence, the electrical properties of carbon nanotubes, it is easy to tailor the electrical properties of these polymerbased FETs, throughout the range from insulating through semiconducting to metallic, through choices of doping levels and chemical manipulation of polymer side chains. A further advantage of doped PANi/PEO nanofibers is that they can be made to draw very small currents and operate at low voltage levels, and thus are promising for applications in which there are requirements to use many FETs to obtain large computational capabilities while minimizing power demands. Fabrication of an experimental FET in this family begins with the preparation of a substrate as follows: A layer of silicon dioxide between 50 and 200 nm thick is deposited on a highly doped (resistivity 0.01 W.cm) silicon substrate, then gold electrodes/contact stripes are deposited on the oxide. Next, one or more fibers of camphorsulphonic acid-doped PANi/PEO having diameters of the order of 100 nm are electrospun onto the substrate so as to span the gap between the gold electrodes (see Figure 1). Figure 2 depicts measured current-versus-voltage characteristics of the device of Figure 1, showing that saturation channel currents occur at source-todrain potentials that are surprisingly low, relative to those of CMOS FETs. The hole mobility in the depletion regime in this transistor was found to be 1.4 10(exp -4) sq cm/(V.s), while the one-dimensional charge density at zero gate bias was estimated to be approximately one hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content of the fibers is expected to enhance the properties of future versions of this transistor.

Theofylaktos, Noulie↗
NASA NTRS1972

On the wide-range bias dependence of transistor d.c. and small-signal current gain factors.

Critical reappraisal of the bias dependence of the dc and small-signal ac current gain factors of planar bipolar transistors over a wide range of currents. This is based on a straightforward consideration of the three basic components of the dc base current arising due to emitter-to-base injected minority carrier transport, base-to-emitter carrier injection, and emitter-base surface depletion layer recombination effects. Experimental results on representative n-p-n and p-n-p silicon devices are given which support most of the analytical findings.

Schmidt, P.↗
NASA NTRS1998

RH1020 Single Event Clock Upset Summary Report

This report summarizes the testing and analysis of "single event clock upset' in the RH1020. Also included are SEU-rate predictions and design recommendations for risk analysis and reduction. The subject of "upsets" in the RH1020 is best understood by using a model consisting of a global clock buffer and a D-type flip-flop as the basic memory unit. The RH1020 is built on the ACT 1 family architecture. As such, it has one low-skew global clock buffer with a TTL-level input threshold that is accessed via a single dedicated pin. The clock signal is driven to full CMOS levels, buffered, and sent to individual row buffers with one buffer per channel. For low-skew performance, the outputs of all of the RH1020 row buffers are shorted together via metal lines, as is done in the A1020B. All storage in the RH1020 consists of routed flip-flops, constructed with multiplexors and feedback through the routing segments. A simple latch can be constructed from a single (combinatorial or C) module; an edge-triggered flip-flop is constructed using two concatenated latches. There is no storage in the I/O modules. The front end of the clock buffering circuitry, at a common point relative to the row buffer, is a sub-circuit that was determined to be the most susceptible to heavy ions. This is due, in part, to its smaller transistors compared to the rest of the circuitry. This conclusion is also supported by SPICE simulations and an analysis of the heavy ion data, described in this report. The edge triggered D flip-flop has two single-event-upset modes. Mode one, called C-module upset, is caused by a heavy ion striking the C-module's sensitive area on the silicon and produces a soft single bit error at the output of the flip-flop. Mode two, called clock upset, is caused by a heavy ion strike on the clock buffer, generating a runt pulse interpreted as a false clock signal and consequently producing errors at the flip-flop outputs. C-module upset sensitivity in the RH1020 is essentially the same as that of its ACT 1 siblings (A1020, A1020A and A1020B), which were well tested, analyzed, and documented in the literature.

Katz, Richard B.↗
NASA NTRS2015

Silicon Carbide (SiC) Power Processing Unit (PPU) for Hall Effect Thrusters

Arkansas Power Electronics International (APEI), Inc., is developing a high-efficiency, radiation-hardened 3.8-kW SiC power supply for the PPU of Hall effect thrusters. This project specifically targets the design of a PPU for the high-voltage Hall accelerator (HiVHAC) thruster, with target specifications of 80- to 160-V input, 200- to 700-V/5A output, efficiency greater than 96 percent, and peak power density in excess of 2.5 kW/kg. The PPU under development uses SiC junction field-effect transistor power switches, components that APEI, Inc., has irradiated under total ionizing dose conditions to greater than 3 MRad with little to no change in device performance.

Reese, Bradley↗
NASA NTRS1993

Characterization of Si (sub X)Ge (sub 1-x)/Si Heterostructures for Device Applications Using Spectroscopic Ellipsometry

Spectroscopic ellipsometry (SE) characterization of several complex Si (sub X)Ge (sub 1-x)/Si heterostructures prepared for device fabrication, including structures for heterojunction bipolar transistors (HBT), p-type and n-type heterostructure modulation doped field effect transistors, has been performed. We have shown that SE can simultaneously determine all active layer thicknesses, Si (sub X)Ge (sub 1-x) compositions, and the oxide overlayer thickness, with only a general knowledge of the structure topology needed a priori. The characterization of HBT material included the SE analysis of a Si (sub X)Ge (sub 1-x) layer deeply buried (600 nanometers) under the silicon emitter and cap layers. In the SE analysis of n-type heterostructures, we examined for the first time a silicon layer under tensile strain. We found that an excellent fit can be obtained using optical constants of unstrained silicon to represent the strained silicon conduction layer. We also used SE to measure lateral sample homogeneity, providing quantitative identification of the inhomogeneous layer. Surface overlayers resulting from prior sample processing were also detected and measured quantitatively. These results should allow SE to be used extensively as a non-destructive means of characterizing Si (sub X)Ge (sub 1-x)/Si heterostructures prior to device fabrication and testing.

Sieg, R. M.↗
NASA NTRS2009

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80 high temperature N-channel MOSFET (metal-oxide semiconductor field-effect transistor) device that was manufactured by CISSOID. This high voltage, medium-power transistor is fabricated using SOI processes and is designed for extreme wide temperature applications such as geothermal well logging, aerospace and avionics, and automotive industry. It has a high DC current capability and is specified for operation in the temperature range of -55 C to +225 C

Patterson, Richard L.↗