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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14

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DOE OSTI2025

Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography

Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination. Here, in this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.

42 ENGINEERING↗

NASA NTRS1982

Process Research on Polycrystalline Silicon Material (PROPSM)

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Culik, J. S.↗

NASA NTRS1983

Process Research on Polycrystalline Silicon Material (PROPSM)

The performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was investigated by measuring the illuminated current voltage (I-V) characteristics of the minicell wafer set. The average short circuit current on different wafers is 3 to 14 percent lower than that of single crystal Czochralski silicon. The scatter was typically less than 3 percent. The average open circuit voltage is 20 to 60 mV less than that of single crystal silicon. The scatter in the open circuit voltage of most of the polycrystalline silicon wafers was 15 to 20 mV, although two wafers had significantly greater scatter than this value. The fill factor of both polycrystalline and single crystal silicon cells was typically in the range of 60 to 70 percent; however several polycrystalline silicon wafers have fill factor averages which are somewhat lower and have a significantly larger degree of scatter.

Culik, J. S.↗

NASA NTRS1984

Development and fabrication of a solar cell junction processing system

A processing system capable of producing solar cell junctions by ion implantation followed by pulsed electron beam annealing was developed and constructed. The machine was to be capable of processing 4-inch diameter single-crystal wafers at a rate of 10(7) wafers per year. A microcomputer-controlled pulsed electron beam annealer with a vacuum interlocked wafer transport system was designed, built and demonstrated to produce solar cell junctions on 4-inch wafers with an AMI efficiency of 12%. Experiments showed that a non-mass-analyzed (NMA) ion beam could implant 10 keV phosphorous dopant to form solar cell junctions which were equivalent to mass-analyzed implants. A NMA ion implanter, compatible with the pulsed electron beam annealer and wafer transport system was designed in detail but was not built because of program termination.

Source record↗

NASA NTRS1995

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Helbaum, Richard F.↗

NASA NTRS1997

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Hellbaum, Richard F.↗

NASA NTRS1997

High Frequency Interconnects on Silicon Substrates

The measured propagation constant of coplanar waveguide (CPW) on silicon wafers as a function of the line dimensions and the resistivity of the Si wafer; CPW on GaAs wafers as a function of the line dimensions, and thin film microstrip (TFMS) polyimide fabricated with polyimide on the surface of a silicon wafer is presented. It is shown that the attenuation of CPW on 2500 Omega-cm Si wafers and-of TFMS with a polyimide thickness of 4 micrometer or greater is comparable to the attenuation of similar lines on GaAs.

Ponchak, George E.↗

NASA NTRS2004

Thin layer composite unimorph ferroelectric driver and sensor

Hellbaum, Richard F.↗

NASA NTRS2008

Embossed Teflon AF Laminate Membrane Microfluidic Diaphragm Valves

A microfluidic system has been designed to survive spaceflight and to function autonomously on the Martian surface. It manipulates microscopic quantities of liquid water and performs chemical analyses on these samples to assay for the presence of molecules associated with past or present living processes. This technology lies at the core of the Urey Instrument, which is scheduled for inclusion on the Pasteur Payload of the ESA ExoMars rover mission in 2013. Fabrication processes have been developed to make the microfabricated Teflon-AF microfluidic diaphragm pumps capable of surviving extreme temperature excursions before and after exposure to liquid water. Two glass wafers are etched with features and a continuous Teflon membrane is sandwiched between them (see figure). Single valves are constructed using this geometry. The microfabricated devices are then post processed by heating the assembled device while applying pneumatic pressure to force the Teflon diaphragm against the valve seat while it is softened. After cooling the device, the embossed membrane retains this new shape. This solves previous problems with bubble introduction into the fluid flow where deformations of the membrane at the valve seat occurred during device bonding at elevated temperatures (100-150 C). The use of laminated membranes containing commercial Teflon AF 2400 sheet sandwiched between spun Teflon AF 1600 layers performed best, and were less gas permeable than Teflon AF 1600 membranes on their own. Spinning Teflon AF 1600 solution (6 percent in FLOURINERT(Registered TradeMark) FC40 solvent, 3M Company) at 500 rpm for 1.5 seconds, followed by 1,000 rpm for 3 seconds onto Borofloat glass wafers, results in a 10-micron-thick film of extremely smooth Teflon AF. This spinning process is repeated several times on flat, blank, glass wafers in order to gradually build a thick, smooth membrane. After running this process at least five times, the wafer and Teflon coating are heated under vacuum at 220 C for one hour in order to drive off any residual solvent present in the composite film. After this, a second blank, glass wafer is brought down from above and the stack is held under vacuum at 3 atm mechanical pressure for ten 10 hours.

Willis, Peter↗

NASA NTRS2010

Simple Check Valves for Microfluidic Devices

A simple design concept for check valves has been adopted for microfluidic devices that consist mostly of (1) deformable fluorocarbon polymer membranes sandwiched between (2) borosilicate float glass wafers into which channels, valve seats, and holes have been etched. The first microfluidic devices in which these check valves are intended to be used are micro-capillary electrophoresis (microCE) devices undergoing development for use on Mars in detecting compounds indicative of life. In this application, it will be necessary to store some liquid samples in reservoirs in the devices for subsequent laboratory analysis, and check valves are needed to prevent cross-contamination of the samples. The simple check-valve design concept is also applicable to other microfluidic devices and to fluidic devices in general. These check valves are simplified microscopic versions of conventional rubber- flap check valves that are parts of numerous industrial and consumer products. These check valves are fabricated, not as separate components, but as integral parts of microfluidic devices. A check valve according to this concept consists of suitably shaped portions of a deformable membrane and the two glass wafers between which the membrane is sandwiched (see figure). The valve flap is formed by making an approximately semicircular cut in the membrane. The flap is centered over a hole in the lower glass wafer, through which hole the liquid in question is intended to flow upward into a wider hole, channel, or reservoir in the upper glass wafer. The radius of the cut exceeds the radius of the hole by an amount large enough to prevent settling of the flap into the hole. As in a conventional rubber-flap check valve, back pressure in the liquid pushes the flap against the valve seat (in this case, the valve seat is the adjacent surface of the lower glass wafer), thereby forming a seal that prevents backflow.

Willis, Peter A.↗

NASA NTRS2013

Fabrication Methods for Adaptive Deformable Mirrors

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Toda, Risaku↗

NASA NTRS2016

Double Sided Si(Ge)/Sapphire/III-Nitride Hybrid Structure

One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.

Park, Yeonjoon↗

NASA NTRS2017

Method of Fabricating Double Sided Si(Ge)/Sapphire/III-Nitride Hybrid Structure

Park, Yeonjoon↗

NASA NTRSDate not supplied

Study of Fallout Metrics for Contamination Analysis

A challenge present in assessing contamination accumulation on many missions is predicting fallout during ground processing given the multiple and various orientations possible for surfaces such as optics and instruments. The best practice assumption has been to quantify particle build up on vertical surfaces as approximately 1/10 that of horizontal surfaces. This fractional relation is important when considering contamination allocations necessary to meet cleanliness requirements since spacecraft can be in many orientations during integration and testing. There is insufficient data to provide confidence in the 1/10 approximation, yet its use can have a significant effect on mission end of life contamination level predictions, leading to expenditures of precious resources to meet mission requirements. A study was conducted to compare and analyze the fallout in horizontal and vertical orientations. Silicon wafers were deployed in four different facilities. Data sets from a long term deployment of wafers were analyzed from a cleanroom facility housing integration of the James Webb Space Telescope (JWST) as well as from a shorter term deployment of wafers in three cleanroom facilities at Goddard Space Flight Center with lower activity. There are many variables influencing the relationship between fallout on vertical and horizontal wafers, including wafer position with respect to air flow, air changes in the facility, duration of exposure, and activity workload. The goal of this continuing study is to develop a tool to inform particulate accumulation predictions for future projects.

Contamination↗

DOE OSTI2024

Innovative recycling of high purity silver from silicon solar cells by acid leaching and ultrasonication

Precious and scarce silver (Ag) is used as a front electrical contact in silicon solar panels. With massive amounts of solar panel waste coming to end-of-life, it is imperative to recover all the Ag from these modules. In this paper, we propose a novel method to easily reclaim Ag from end-of-life silicon solar cells using low concentration sulfuric acid (H 2 SO 4 ) leaching followed by ultrasonication. Our process simplifies the Ag recycling procedure by directly recovering the Ag contacts from solar cells, eliminating the need for secondary precipitation/electrodeposition. First, scanning electron microscopy (SEM) with energy dispersive X-ray spectroscopy (EDX) and X-ray photoelectron spectroscopy (XPS) was used to study the leaching and ultrasonication process on rejected solar wafers. Next, a solar panel from landfill was heated in a furnace to burn off the polymer encapsulant. The silicon wafers were then collected from the burning process and leached in 2 M H 2 SO 4 at two different shaking speeds for 48 hours at room temperature. Finally, the end-of-life silicon wafer pieces were collected, sonicated in water, and then the sonication water was centrifuged to show a proof-of-concept to recover the Ag contacts. Inductively coupled plasma optical emission spectroscopy (ICPOES) is used to monitor dissolved elements in the leachate as a function of time and shaking speed. XPS is used to evaluate the composition of the silicon cell wafer surface before and after H 2 SO 4 leaching. SEM is used to image the recovered Ag contacts morphology and EDX confirms the recovered particles contain high amounts of Ag. Furthermore, a proposed schematic illustrates the authors’ hypothesis for the peeling mechanism.

14 SOLAR ENERGY↗

DOE OSTI2025

Low embodied energy and carbon, high lifetime silicon boules via a combined chemical vapor deposition/float zone process

This work evaluates a new process route to making float zone (Fz)-quality silicon wafers using a combination of computational fluid dynamics (CFD) modeling and technoeconomic analysis. Our analysis finds that the new process competes with Czochralski (Cz)-grown wafers on a levelized cost of energy system level. The new process also decreases embodied energy and carbon of silicon photovoltaics (PV) by ~6x circumventing the energy-costly Siemens process used in polycrystalline silicon (poly-Si) production plants to generate feedstock for Fz and Cz boules. Instead of using poly-Si from the Siemens process to feed crystallization, the new process uses the high-purity, trichlorosilane (TCS) precursor gas to grow a poly-Si feed rod in-situ during a modified Fz1,2 boule growth process. The gas-to-boule float zone process enables opportunity to produce high-purity (low metals and oxygen content), uniformly doped single crystal silicon boules and wafers with high bulk lifetimes (τ bulk > 15 ms) to enable higher efficiency cells (>27 %) with fewer known degradation mechanisms than Czochralski (Cz)-grown wafers. These benefits reduce the levelized cost of electricity (LCOE) of PV-produced electricity. Here we show the results of our CFD and chemical modeling of the process to prove feasibility and economic viability.

14 SOLAR ENERGY↗

DOE OSTI2024

Continuously tunable uniaxial strain control of van der Waals heterostructure devices

Uniaxial strain has been widely used as a powerful tool for investigating and controlling the properties of quantum materials. However, existing strain techniques have so far mostly been limited to use with bulk crystals. Although recent progress has been made in extending the application of strain to two-dimensional van der Waals (vdW) heterostructures, these techniques have been limited to optical characterization and extremely simple electrical device geometries. Here, we report a piezoelectric-based in situ uniaxial strain technique enabling simultaneous electrical transport and optical spectroscopy characterization of dual-gated vdW heterostructure devices. Critically, our technique remains compatible with vdW heterostructure devices of arbitrary complexity fabricated on conventional silicon/silicon dioxide wafer substrates. We demonstrate a large and continuously tunable strain of up to –0.15% at millikelvin temperatures, with larger strain values also likely achievable. We quantify the strain transmission from the silicon wafer to the vdW heterostructure, and further demonstrate the ability of strain to modify the electronic properties of twisted bilayer graphene. Our technique provides a highly versatile new method for exploring the effect of uniaxial strain on both the electrical and optical properties of vdW heterostructures and can be easily extended to include additional characterization techniques.

Electrical properties and parameters↗

DOE OSTI2026

A Path to III-V Photovoltaic Cost Reduction Combining GaAs (211) Spalling with Halide Vapor Phase Epitaxy

This presentation is an overview of the following, Spalling on 211 oriented wafers produces flat surface without faceting: 1) Demonstrated spall on entire 2" wafer; 2) GaAs and GaInP grown on 211 wafers by HVPE; and 3) Promising cell with VOC=1.02 V and IQE-1. Next steps: 1) Grow cell on spalled wafer and 2) Growth studies to improve material and cell on 211 substrates.

14 SOLAR ENERGY↗