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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 253 records · Page 14
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

A 32-GHz solid-state power amplifier for deep space communications

A 1.5-W solid-state power amplifier (SSPA) has been demonstrated as part of an effort to develop and evaluate state-of-the-art transmitter and receiver components at 32 and 35 GHz for future deep space missions. Output power and efficiency measurements for a monolithic millimeter-wave integrated circuit (MMIC)-based SSPA are reported. Technical design details for the various modules and a thermal analysis are discussed, as well as future plans.

Wamhof, P. D.↗
NASA NTRS1996

Instrument For Simulation Of Piezoelectric Transducers

Electronic instrument designed to simulate dynamic output of integrated-circuit piezoelectric acceleration or pressure transducer. Operates in conjunction with external signal-conditioning circuit, generating square-wave signal of known amplitude for use in calibrating signal-conditioning circuit. Instrument also useful as special-purpose square-wave generator in other applications.

Mcnichol, Randal S.↗
NASA NTRS1995

Separation and Detection of Toxic Gases with a Silicon Micromachined Gas Chromatography System

A miniature gas chromatography (GC) system was designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 microliter sample loop; a 0.9 meter long, rectangular shaped (300 micrometer width and 10 micrometer height) capillary column coated with a 0.2 micrometer thick copper phthalocyanine (CuPc) stationary phase; and a dual detector scheme based upon a CuPc-coated chemiresistor and a commercially available 125 micrometer diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex (r) cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts-per-million (ppm) concentrations of ammonia (NH3) and nitrogen dioxide (NO2) when isothermally operated (55-80 degrees C). With a helium carrier gas and nitrogen diluent, a 10 microliter sample volume containing ammonia and nitrogen dioxide injected at 40 psi ((2.8 x 10(exp 5)Pa)) can be separated in less than 30 minutes.

Kolesar, Edward S.↗
NASA NTRS1997

Root-Raised Cosine Filter Implementation That Uses Canonical Signed Digits for High-Speed Digital Filter Applications

NASA Lewis Research Center's Space Communications Division has been investigating high-speed digital filters that can operate at a higher speed than those in current use for a digital modulator and demodulator (modem). Using the Canonical Signed Digits (CSD) number representation for filter coefficients is a very effective way to increase the filter's speed while reducing complexity in the digital filter hardware design. This approach is a good alternative to using an expensive parallel-processing design technique or custom, application-specific integrated circuits. Such integrated circuits may not be suitable for applications that require filter speeds faster than what application-specific integrated circuits digital signal processors can offer for a dedicated channel. When a communication channel is a dedicated, multiplication process--a costly, time-consuming process--it can be greatly simplified by a replacement of the filter coefficients with CSD numbers. A computer code written with the MATLAB software package runs the program and generates CSD-represented filter coefficients that are based on minimizing minimum mean square errors. Also, the Alta Group of Cadence's Signal Processing Workstation is used to simulate and analyze the CSD filter responses. The impulse response of the root-raised cosine filter that is used as a base model is defined. From this filter, a set of coefficients is sampled and stored in a file. For the all coefficients, the optimal CSD number for each coefficient is searched on the basis of the minimum-mean-square-errors criterion. Because the distribution of CSD numbers is not uniform, quantization errors tend to be bigger for coefficients greater than 1/2. To offset errors that occur in a region of coefficients between 1/2 to 1 and to better represent fractions with CSD numbers, an extra nonzero digit is allowed for any coefficients exceeding 1/2. This will greatly improve frequency response as well as intersymbol interference at the receiver. The frequency response of a set of collected CSD-represented filter coefficients was compared with the same filter that was conventionally implemented. Analyses show CSD-implemented filters perform as well as conventional filters. Comparison of eye diagrams and bit-error-rate curves between CSD filters and traditionally implemented filters are almost indistinguishable. However, filter complexity was reduced from almost 3.5 to 1 for CSD filters. Complete computer simulation results are available. In the near future, work will focus on building actual working digital filter hardware in a field programmable gate array (FPGA).

Kim, Heechul↗
NASA NTRS2009

100-GHz Phase Switch/Mixer Containing a Slot-Line Transition

A circuit that can function as a phase switch, frequency mixer, or frequency multiplier operates over a broad frequency range in the vicinity of 100 GHz. Among the most notable features of this circuit is a grounded uniplanar transition (in effect, a balun) between a slot line and one of two coplanar waveguides (CPWs). The design of this circuit is well suited to integration of the circuit into a microwave monolithic integrated circuit (MMIC) package. One CPW is located at the input end and one at the output end of the top side of a substrate on which the circuit is fabricated (see Figure 1). The input CPW feeds the input signal to antiparallel flip-chip Schottky diodes connected to the edges of the slot line. Phase switching is effected by the combination of (1) the abrupt transition from the input CPW to the slot line and (2) CPW ground tuning effected by switching of the bias on the diodes. Grounding of the slot metal to the bottom metal gives rise to a frequency cutoff in the slot. This cutoff is valuable for separating different frequency components when the circuit is used as a mixer or multiplier. Proceeding along the slot line toward the output end, one encounters the aforementioned transition, which couples the slot line to the output CPW. Impedance tuning of the transition is accomplished by use of a high-impedance section immediately before the transition.

Gaier, Todd↗
NASA NTRS2008

Three-Stage InP Submillimeter-Wave MMIC Amplifier

A submillimeter-wave monolithic integrated- circuit (S-MMIC) amplifier has been designed and fabricated using an indium phosphide (InP) 35-nm gate-length high electron mobility transistor (HEMT) device, developed at Northrop Grumman Corporation. The HEMT device employs two fingers each 15 micrometers wide. The HEMT wafers are grown by molecular beam epitaxy (MBE) and make use of a pseudomorphic In0.75Ga0.25As channel, a silicon delta-doping layer as the electron supply, an In0.52Al0.48As buffer layer, and an InP substrate. The three-stage design uses coplanar waveguide topology with a very narrow ground-to-ground spacing of 14 micrometers. Quarter-wave matching transmission lines, on-chip metal-insulator-metal shunt capacitors, series thin-film resistors, and matching stubs were used in the design. Series resistors in the shunt branch arm provide the basic circuit stabilization. The S-MMIC amplifier was measured for S-parameters and found to be centered at 320 GHz with 13-15-dB gain from 300-345 GHz. This chip was developed as part of the DARPA Submillimeter Wave Imaging Focal Plane Technology (SWIFT) program (see figure). Submillimeter-wave amplifiers could enable more sensitive receivers for earth science, planetary remote sensing, and astrophysics telescopes, particularly in radio astronomy, both from the ground and in space. A small atmospheric window at 340 GHz exists and could enable ground-based observations. However, the submillimeter-wave regime (above 300 GHz) is best used for space telescopes as Earth s atmosphere attenuates most of the signal through water and oxygen absorption. Future radio telescopes could make use of S-MMIC amplifiers for wideband, low noise, instantaneous frequency coverage, particularly in the case of heterodyne array receivers.

Pukala, David↗
NASA NTRS2003

Parallel Subconvolution Filtering Architectures

These architectures are based on methods of vector processing and the discrete-Fourier-transform/inverse-discrete- Fourier-transform (DFT-IDFT) overlap-and-save method, combined with time-block separation of digital filters into frequency-domain subfilters implemented by use of sub-convolutions. The parallel-processing method implemented in these architectures enables the use of relatively small DFT-IDFT pairs, while filter tap lengths are theoretically unlimited. The size of a DFT-IDFT pair is determined by the desired reduction in processing rate, rather than on the order of the filter that one seeks to implement. The emphasis in this report is on those aspects of the underlying theory and design rules that promote computational efficiency, parallel processing at reduced data rates, and simplification of the designs of very-large-scale integrated (VLSI) circuits needed to implement high-order filters and correlators.

Gray, Andrew A.↗
NASA NTRS2015

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

JFET↗
NASA NTRS1995

Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

Mehdi, Imran↗
NASA NTRS1981

A high capacity satellite switched TDMA microwave switch matrix

A description is given of the conceptual design of a high-capacity satellite switched-time division multiple access (SS-TDMA) microwave switch matrix fabricated with GaAs monolithic microwave integrated circuits (MMICs), including integration of both microwave and control logic circuits into the monolithic design. The technology required for a 30/20 GHz communications system includes an on-board SS-TDMA switch matrix. A conceptual design study that has been completed for a wideband, high-capacity (typically 100 x 100) channel switch matrix using technology anticipated for 1987 is described, noting that the study resulted in a switch matrix design concept using a coupled crossbar architecture implemented with MMIC. The design involves basic building block MMIC, permitting flexible growth and efficient wraparound redundancy to increase reliability.

Cory, B. J.↗
NASA NTRS2009

Waveguide Transition for Submillimeter-Wave MMICs

An integrated waveguide-to-MMIC (monolithic microwave integrated circuit) chip operating in the 300-GHz range is designed to operate well on high-permittivity semiconductor substrates typical for an MMIC amplifier, and allows a wider MMIC substrate to be used, enabling integration with larger MMICs (power amplifiers). The waveguide-to- CBCPW (conductor-backed coplanar waveguide) transition topology is based on an integrated dipole placed in the E-plane of the waveguide module. It demonstrates low loss and good impedance matching. Measurement and simulation demonstrate that the loss of the transition and waveguide loss is less than 1-dB over a 340-to-380-GHz bandwidth. A transition is inserted along the propagation direction of the waveguide. This transition uses a planar dipole aligned with the maximum E-field of the TE10 waveguide mode as an inter face between the waveguide and the MMIC. Mode conversion between the coplanar striplines (CPS) that feed the dipole and the CBCPW transmission line is accomplished using a simple air-bridge structure. The bottom side ground plane is truncated at the same reference as the top-side ground plane, leaving the end of the MMIC suspended in air.

Leong, Kevin M.↗
NASA NTRS1993

Total Ionizing Dose Effects in 12-Bit Successive-Approximation Analog-To-Digital Converters

Analog-to-digital (A/D) converters are critical components in many space and military systems, and there have been numerous advances in A/D converter technology that have increased the resolution and conversion time. The increased performance is due to two factors: (1) advances in circuit design and complexity, which have increased the number of components and the integration density; and (2) new process technologies, such as BiCMOS, which provide better performance, cost, and smaller size in mixed-signal circuits. High-speed A/D converters, with conversion rates above 1 MHz, present a challenge to circuit designers and test engineers. Their complex architectures and high-performance specifications result in numerous possible failure modes when they are subjected to ionizing radiation. The dominant failure mode may depend on the specific application because the fundamental effects on MOS and bipolar transistors are strongly affected by bias conditions.

Lee, C. I.↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1986

Multiplier Architecture for Coding Circuits

Multipliers based on new algorithm for Galois-field (GF) arithmetic regular and expandable. Pipeline structures used for computing both multiplications and inverses. Designs suitable for implementation in very-large-scale integrated (VLSI) circuits. This general type of inverter and multiplier architecture especially useful in performing finite-field arithmetic of Reed-Solomon error-correcting codes and of some cryptographic algorithms.

Wang, C. C.↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1986

A design concept for an MMIC microstrip phased array

A conceptual design for a microstrip phased array with monolithic microwave integrated circuit (MMIC) amplitude and phase controls is described. The MMIC devices used are 20 GHz variable power amplifiers and variable phase shifters recently developed by NASA contractors for applications in future Ka band advanced satellite communication antenna systems. The proposed design concept is for a general NxN element array of rectangular lattice geometry. Subarray excitation is incorporated in the MMIC phased array design to reduce the complexity of the beam forming network and the number of MMIC components required. The proposed design concept takes into consideration the RF characteristics and actual phyical dimensions of the MMIC devices. Also, solutions to spatial constraints and interconnections associated with currently available packaging designs are discussed. Finally, the design of the microstrip radiating elements and their radiation characteristics are examined.

Lee, R. Q.↗