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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Low-temperature emergent neuromorphic networks with correlated oxide devices

Significance Designing neuromorphic hardware for cryoelectronics is an important area of research as the field of computing paradigms beyond complementary metal-oxide-semiconductor (CMOS) progresses. Superconductivity and metal−insulator transitions are two of the most celebrated emergent, collective properties found in quantum materials such as strongly correlated oxides. Here, we present simulations of artificial neural networks that can be designed by combining superconducting devices (e.g. Josephson junctions) with Mott metal−insulator transition−based tunable resistor devices. Our simulations show that 1) neurons and synapses can be seamlessly created, 2) their functions can be tuned via learning, and 3) controlling disorder by incorporating light ions enables exponential multiplicity of states. The results open up directions for incorporating emergent behavior seen in condensed matter into hardware design for artificial intelligence.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Metal Chalcogenides for Neuromorphic Computing: Emerging Materials and Mechanisms

The approaching end of Moore's Law scaling has significantly accelerated multiple fields of research including neuromorphic-, quantum-, and photonic computing, each of which possesses unique benefits unobtained through conventional binary computers. One of the most compelling arguments for neuromorphic computing systems is power consumption, noting that computations made in the human brain are approximately 106 times more efficient than conventional CMOS logic. This review article focuses on the materials science and physical mechanisms found in metal chalcogenides that are currently being explored for use in neuromorphic applications. We begin by reviewing the key biological signal generation and transduction mechanisms within neuronal components of mammalian brains and subsequently compare with observed experimental measurements in chalcogenides. With robustness and energy efficiency in mind, we will focus on short-range mechanisms such as structural phase changes and correlated electron systems that can be driven by low-energy stimuli, such as temperature or electric field. We aim to highlight fundamental materials research and existing gaps that need to be overcome to enable further integration or advancement of metal chalcogenides for neuromorphic systems.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Electric-field-induced crossover of polarization reversal mechanisms in Al 1–x Sc x N ferroelectrics

Scandium-doped aluminum nitride, Al 1–x Sc x N, represents a new class of displacive ferroelectric materials with high polarization and sharp hysteresis along with high-temperature resilience, facile synthesizability and compatibility with standard CMOS fabrication techniques. The fundamental physics behind the transformation of unswitchable piezoelectric AlN into switchable Al–Sc–N ferroelectrics depends upon important atomic properties such as local structure, dopant distributions and the presence of competing mechanism of polarization switching in the presence of an applied electric-field that have not been understood. We computationally synthesize Al 1–x Sc x N to quantify the inhomogeneity of Sc distribution and phase segregation, and characterize its crystal and electronic structure as a function of Sc-doping. Nudged elastic band calculations of the potential energy surface and quantum molecular dynamics simulations of direct electric-field-driven ferroelectric switching reveal a crossover between two polarization reversal mechanisms—inhomogeneous nucleation-and-growth mechanism originating near Sc-rich regions in the limit of low applied fields and nucleation-limited-switching in the high-field regime. Finally, understanding polarization reversal pathways for these two mechanisms as well as the role of local Sc concentration on activation barriers provides design rules to identify other combinations of dopant elements, such as Zr, Mg etc. to synthesize superior AlN-based ferroelectric materials.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2024

Properties of Nb x Ti (1–x) N thin films deposited on 300 mm silicon wafers for upscaling superconducting digital circuits

Scaling superconducting digital circuits requires fundamental changes in the current material set and fabrication process. The transition to 300 mm wafers and the implementation of advanced lithography are instrumental in facilitating mature CMOS processes, ensuring uniformity, and optimizing the yield. Here, this study explores the properties of Nb x Ti (1–x) N films fabricated by magnetron DC sputtering on 300 mm Si wafers. As a promising alternative to traditional Nb in device manufacturing, Nb x Ti (1–x) N offers numerous advantages, including enhanced stability and scalability to smaller dimensions, in both processing and design. As a ternary material, Nb x Ti (1–x) N allows engineering material parameters by changing deposition conditions. The engineered properties can be used to modulate device parameters through the stack and mitigate failure modes. We report characterization of Nb x Ti (1–x) N films at less than 2% thickness variability, 2.4% T c variability and 3% composition variability. Film resistivity (140–375 Ωcm) shows a strong correlation with the film oxygen content, while the critical temperature T c (4.6 K–14.1 K) is strongly affected by film stoichiometry and its microstructure has only a moderate effect on modifying T c . Our results offer insights about the interplay between film stoichiometry, film microstructure and critical temperature.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

Strategies for on-chip digital data compression for X-ray pixel detectors

Here, the continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of >1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12x.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. Finally, the measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 x16 pixel matrix.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

A 20 Gbps PAM4 data transmitter ASIC for particle physics experiments

We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS technology. Two serializers share a 5.12 GHz Phase Locked Loop (PLL) clock. The outputs from the serializers are combined into a PAM4 signal that directly drives a Vertical-Cavity-Surface-Emitting-Laser (VCSEL). The input data channels, each at 1.28 Gbps, are scrambled with an internal 2$^{7}$-1 Pseudo-Random Binary Sequence (PRBS), which also serves as a frame aligner. GBS20 is tested to work at 10.24 and 20.48 Gbps with a VCSEL-based Transmitter-Optical-Subassembly (TOSA). The power consumption of GBS20 is below 238 mW and reduced to 164 mW in the low-power mode.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

A radiation tolerant clock generator for the CMS endcap timing layer readout chip

Here, we present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm 2 /mg.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

A high-resolution clock phase shifter circuitry for ALTIROC

Abstract A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 µm × 248 µm. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are ±0.6 LSB and ±0.75 LSB, respectively. The jitter from −25 °C to 20 °C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.

Instruments & Instrumentation↗
DOE OSTI2023

First test results of the trans-impedance amplifier stage of the ultra-fast HPSoC ASIC

Abstract We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 μm thick AC-LGAD. The evaluation of the analog front end with β-particles impinging on 3 × 3 AC-LGAD arrays (500 μm pitch, 200 × 200 μm 2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplification stages to reach a jitter of 15 ps.

Instruments & Instrumentation↗
DOE OSTI2023

The COLUTA ADC ASIC and the ATLAS HL-LHC Liquid Argon Front-End Readout

Abstract The upgraded High-Luminosity Large Hadron Collider (HL-LHC) requires a new radiation tolerant ATLAS Liquid Argon (LAr) Calorimeter readout operating at 40 MHz with 16-bit dynamic range. The Front-End Board 2 (FEB2) will provide the front-end readout for the calorimeter, and will interface a series of custom ASICs due to radiation tolerance requirements of the HL-LHC. The COLUTA is a 65 nm CMOS custom 8-channel 15-bit 40 MSPS ADC ASIC developed for this application. This contribution will present performance results of the final prototype of the COLUTA, surpassing specifications at >11.5 ENOB for relevant frequencies, as well as non-linearity and radiation requirements. Preliminary integration results of the front-end readout components will also be described by means of the FEB2 Pre-Prototype, the “Slice Testboard”.

Instruments & Instrumentation↗
DOE OSTI2022

A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

First test results of the HGCAL concentrator ASICs: ECON-T and ECON-D

With over 6 million channels, the High Granularity Calorimeter for the CMS HL-LHC upgrade presents a unique data transmission challenge. The ECON ASICs provide a critical stage of on-detector data compression and selection for the trigger path (ECON-T) and data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65 nm CMOS, are radiation tolerant up to 200 Mrad and require low power consumption: < 2.5 mW/sensor-channel per chip. Here, we report on the first functionality and radiation tests for the ECON-D-P1 full-functionality prototype. We present a comparison of single event effect (SEE) cross sections measured for different methods of triple modular redundancy using test results from the ECON-T-P1 full-functionality prototype.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

GRAPH — an readout ASIC for large MCP based detectors

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

An integer- N frequency synthesizer for flexible on-chip clock generation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

47 OTHER INSTRUMENTATION↗