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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Xyce™ Parallel Electronic Simulator Users’ Guide, Version 7.8

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: (1) Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. (2) A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. (3) Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). (4) Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

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DOE OSTI2024

Xyce™ Parallel Electronic Simulator Users' Guide (V.7.9)

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: • Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. • A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. • Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). • Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

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DOE OSTI2025

Xyce™ Parallel Electronic Simulator Users’ Guide, Version 7.10

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: • Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. • A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. • Device models that are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). • Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase — a message passing parallel implementation — which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1979

Development of high reliability, high frequency power conditioning models of converter regulators

High efficiency conversion, regulation, and filtering techniques are discussed for power using high conversion frequencies; i.e., in the order of 1 to 5 MHz for converters having total output power capability in the order of 20 watts and 200 to 500 KHz for converters having total output powers in excess of 200 watts. Work centered on areas of component selection, material selection, optimization of the various types of circuits required, and the selection of materials for and design of magnetic components. These techniques were then applied to the design of two sample converters, one a medium power instrument type converter and the second a high power converter representative of a primary spacecraft converter regulator. The configuration and performance of the two converters is reported and discussed.

Rochussen, A. W.↗
NASA NTRS1995

Dry and wet arc track propagation resistance testing

The wet arc-propagation resistance test for wire insulation provides an assessment of the ability of an insulation to prevent damage in an electrical environment. Results of an arc-propagation test may vary slightly due to the method of arc initiation; therefore a standard test method must be selected to evaluate the general arc-propagation resistance characteristics of an insulation. This test method initiates an arc by dripping salt water over pre-damaged wires which creates a conductive path between the wires. The power supply, test current, circuit resistances, and other variables are optimized for testing 20 guage wires. The use of other wire sizes may require modifications to the test variables. The dry arc-propagation resistance test for wire insulation also provides an assessment of the ability of an insulation to prevent damage in an electrical arc environment. In service, electrical arcs may originate form a variety of factors including insulation deterioration, faulty installation, and chafing. Here too, a standard test method must be selected to evaluate the general arc-propagation resistance characteristics of an insulation. This test method initiates an arc with a vibrating blade. The test also evaluates the ability of the insulation to prevent further arc-propagation when the electrical arc is re-energized.

Beach, Rex↗
NASA NTRS2002

Overall Traveling-Wave-Tube Efficiency Improved By Optimized Multistage Depressed Collector Design

Depressed Collector Design The microwave traveling wave tube (TWT) is used widely for space communications and high-power airborne transmitting sources. One of the most important features in designing a TWT is overall efficiency. Yet, overall TWT efficiency is strongly dependent on the efficiency of the electron beam collector, particularly for high values of collector efficiency. For these reasons, the NASA Glenn Research Center developed an optimization algorithm based on simulated annealing to quickly design highly efficient multistage depressed collectors (MDC's). Simulated annealing is a strategy for solving highly nonlinear combinatorial optimization problems. Its major advantage over other methods is its ability to avoid becoming trapped in local minima. Simulated annealing is based on an analogy to statistical thermodynamics, specifically the physical process of annealing: heating a material to a temperature that permits many atomic rearrangements and then cooling it carefully and slowly, until it freezes into a strong, minimum-energy crystalline structure. This minimum energy crystal corresponds to the optimal solution of a mathematical optimization problem. The TWT used as a baseline for optimization was the 32-GHz, 10-W, helical TWT developed for the Cassini mission to Saturn. The method of collector analysis and design used was a 2-1/2-dimensional computational procedure that employs two types of codes, a large signal analysis code and an electron trajectory code. The large signal analysis code produces the spatial, energetic, and temporal distributions of the spent beam entering the MDC. An electron trajectory code uses the resultant data to perform the actual collector analysis. The MDC was optimized for maximum MDC efficiency and minimum final kinetic energy of all collected electrons (to reduce heat transfer). The preceding figure shows the geometric and electrical configuration of an optimized collector with an efficiency of 93.8 percent. The results show the improvement in collector efficiency from 89.7 to 93.8 percent, resulting in an increase of three overall efficiency points. In addition, the time to design a highly efficient MDC was reduced from a month to a few days. All work was done in-house at Glenn for the High Rate Data Delivery Program. Future plans include optimizing the MDC and TWT interaction circuit in tandem to further improve overall TWT efficiency.

Vaden, Karl R.↗
NASA NTRS2006

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Shuler, Robert L.↗
NASA NTRS2015

Conformal and Spectrally Agile Ultra Wideband Phased Array Antenna for Communication and Sensing

There is a continuing need for reducing size and weight of satellite systems, and is also strong interest to increase the functional role of small- and nano-satellites (for instance SmallSats and CubeSats). To this end, a family of arrays is presented, demonstrating ultra-wideband operation across the numerous satellite communications and sensing frequencies up to the Ku-, Ka-, and Millimeter-Wave bands. An example design is demonstrated to operate from 3.5-18.5 GHz with VSWR2 at broadside, and validated through fabrication of an 8 x 8 prototype. This design is optimized for low cost, using Printed Circuit Board (PCB) fabrication. With the same fabrication technology, scaling is shown to be feasible up to a 9-49 GHz band. Further designs are discussed, which extend this wideband operation beyond the Ka-band, for instance from 20-80 GHz. Finally we will discuss recent efforts in the direct integration of such arrays with digital beamforming back-ends. It will be shown that using a novel on-site coding architecture, orders of magnitude reduction in hardware size, power, and cost is accomplished in this transceiver.

Ultra Wideband antenna↗
DOE OSTI2021

Quantum Solver of Contracted Eigenvalue Equations for Scalable Molecular Simulations on Quantum Computing Devices

The accurate computation of ground and excited states of many-fermion quantum systems is one of the most consequential, contemporary challenges in the physical and computational sciences whose solution stands to benefit significantly from the advent of quantum computing devices. Existing methodologies using phase estimation or variational algorithms have potential drawbacks such as deep circuits requiring substantial error correction or non-trivial high-dimensional classical optimization. In this work, we introduce a quantum solver of contracted eigenvalue equations, the quantum analogue of classical methods for the energies and reduced density matrices of ground and excited states. The solver does not require deep circuits or difficult classical optimization and achieves an exponential speed-up over its classical counterpart. We demonstrate the algorithm though computations on both a quantum simulator and two IBM quantum processing units.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Infidelity Associated with Eliminating the Bus Resonator

This summer project started out to quantify the error associated with an approximate model of a superconducting circuit, where two qubits are dispersively coupled through a bus resonator. Understanding this error helps us decide if the approximate model is sufficient for the purpose of optimal control. We find out that the error of the approximate model covers up a nontrivial problem of the underlying circuit, which limits the fidelity of two-qubit gates under 99% for practical parameters. This suggests that high fidelity gates of this circuit cannot be achieved through optimal control alone, and changes of the parameters/design of the circuits appear necessary. Additionally, to carry out the algebra involved, a symbolic commutator algebra package HamMaker is developed in Julia. The package is capable of automating some difficult algebra in optimal control that previously had to be performed by hand. Within this work, HamMaker has been used to derived some simple but nontrivial corrections to the existing effective Hamiltonian.

74 ATOMIC AND MOLECULAR PHYSICS↗
NASA NTRS2016

A Discrete Component Low-Noise Preamplifier Readout for a Linear (1x16) SiC Photodiode Array

A compact, low-noise and inexpensive preamplifier circuit has been designed and fabricated to optimally readout a common cathode (1x16) channel 4H-SiC Schottky photodiode array for use in ultraviolet experiments. The readout uses an operational amplifier with 10 pF capacitor in the feedback loop in parallel with a low leakage switch for each of the channels. This circuit configuration allows for reiterative sample, integrate and reset. A sampling technique is given to remove Johnson noise, enabling a femtoampere level readout noise performance. Commercial-off-the-shelf acquisition electronics are used to digitize the preamplifier analogue signals. The data logging acquisition electronics has a different integration circuit, which allows the bandwidth and gain to be independently adjusted. Using this readout, photoresponse measurements across the array between spectral wavelengths 200 nm and 370 nm are made to establish the array pixels external quantum efficiency, current responsivity and noise equivalent power.

low-noise preamplifier↗
DOE OSTI2022

VQE method: a short survey and recent developments

Abstract The variational quantum eigensolver (VQE) is a method that uses a hybrid quantum-classical computational approach to find eigenvalues of a Hamiltonian. VQE has been proposed as an alternative to fully quantum algorithms such as quantum phase estimation (QPE) because fully quantum algorithms require quantum hardware that will not be accessible in the near future. VQE has been successfully applied to solve the electronic Schrödinger equation for a variety of small molecules. However, the scalability of this method is limited by two factors: the complexity of the quantum circuits and the complexity of the classical optimization problem. Both of these factors are affected by the choice of the variational ansatz used to represent the trial wave function. Hence, the construction of an efficient ansatz is an active area of research. Put another way, modern quantum computers are not capable of executing deep quantum circuits produced by using currently available ansatzes for problems that map onto more than several qubits. In this review, we present recent developments in the field of designing efficient ansatzes that fall into two categories—chemistry–inspired and hardware–efficient—that produce quantum circuits that are easier to run on modern hardware. We discuss the shortfalls of ansatzes originally formulated for VQE simulations, how they are addressed in more sophisticated methods, and the potential ways for further improvements.

Fedorov, Dmitry A. (ORCID:0000000316598580)↗
NASA NTRSDate not supplied

QuAIL Tools for Benchmarking, Analysis and Quantum Algorithm Development

HybridQ and PySA are open-source tools developed by NASA to support benchmarking, analysis and quantum algorithm development in areas such as simulation, optimization and machine learning. These tools leverage classical hardware acceleration via high-performance computing CPU and GPU architectures and support high-performance computing. HybridQ is a highly extensible platform designed to provide a common framework to integrate multiple state-of-the-art techniques to simulate large scale quantum circuits. PySA is an extensible platform to optimize a classical cost function. We provide an outline of each of these open-source tools and highlight projects using each of these tools in contexts of simulation, optimization and machine learning.

Quantum Computing↗
DOE OSTI2024

LENS: Learning Enabled Network Synthesis

RTRC and UMD have developed novel machine learning based methods under the ARPA-E DIFFERENTIATE program for rapid acceleration of hypothesis generation in complex architecture design spaces involving both discrete choices of component inclusion and interconnection and continuous parametric decisions. The project named Learning Enabled Network Synthesis (LENS) further demonstrated the developed methods on challenging electrical power converter design problems by identifying the most suitable circuit topologies and simultaneously selecting the most appropriate components to achieve optimized design of power converter with improved performances. We demonstrated that LENS could enable exploration of very large design space of circuit topologies and components by addressing the limitations of conventional design process in non-linear, high switching speed, multi-dimensional power converter design and optimization. The key innovation developed in LENS is the seamless integration of statistical learning and logical reasoning techniques and building on the individual strengths of these techniques for rapid hypothesis discovery. The main component of LENS comprises of: 1) Graph Reasoning Engine (GRE) to enforce composition rules that rapidly reject all discrete architectures that are composed incorrectly and generates an adaptive database of feasible designs which can be used by ML modules, 2) Graph Generative Learning module which is a deep neural network based generative model for graph architectures which can enable design space exploration beyond the dataset generated by the GRE, 3) Graph Reduced Order Model (ROM) for graph domains for accelerating computation of output metrics, and 4) Active learning and Rule Discovery module for sample efficient learning and extracting logical rules from the learned ML models which will be integrated in the GRE to enhance the filtering effectiveness. LENS approach can be applied to any design domains where designs can be represented as multi-attribute graphs. The LENS team integrated the various technical innovations listed above into an optimization pipeline and exercised the optimization pipeline on the converter design problem. The LENS project demonstrated that the developed AI/ML technologies can be used to generate novel converter circuits >45x faster than experts on chosen use-cases. This can enable faster design space exploration and identification of new designs which are not considered by experts due to the increasing design space complexity. This has significant potential impact on the public and energy needs of the country. It is currently estimated that 30% of all electrical powers generated passes through power converters. The future estimate is that 80% of all power generated would be passing through converters. LENS fills a critical gap in this space since by accelerating the design process the designers would be able to generate more efficient converters which can lead to significant energy savings for the country.

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DOE OSTI2023

A Novel Spatial-Temporal Variational Quantum Circuit to Enable Deep Learning on NISQ Devices

Quantum computing presents a promising approach for machine learning with its capability for extremely parallel computation in high-dimension through superposition and entanglement. Despite its potential, existing quantum learning algorithms, such as Variational Quantum Circuits (VQCs), face challenges in handling more complex datasets, particularly those that are not linearly separable. What’s more, it encounters the deployability issue, making the learning models suffer a drastic accuracy drop after deploying them to the actual quantum devices. To overcome these limitations, this paper proposes a novel spatial-temporal design, namely “ST-VQC”, to integrate nonlinearity in quantum learning and improve the robustness of the learning model to noise. Specifically, ST-VQC can extract spatial features via a novel block-based encoding quantum sub-circuit coupled with a layer-wise computation quantum sub-circuit to enable temporal-wise deep learning. Additionally, a SWAP-Free physical circuit design is devised to improve robustness. These designs bring a number of hyperparameters. After a systematic analysis of the design space for each design component, an automated optimization framework is proposed to generate the ST-VQC quantum circuit. The proposed ST-VQC has been evaluated on two IBM quantum processors, ibm-cairo with 27 qubits and ibmq-lima with 7 qubits to assess its effectiveness. The results of the evaluation on the standard dataset for binary classification show that ST-VQC can achieve over 30% accuracy improvement compared with existing VQCs on actual quantum computers. Moreover, on a non-linear synthetic dataset, the STVQC outperforms a linear classifier by 27.9%, while the linear classifier using classical computing outperforms the existing VQC by 15.58%.

Li, Jinyang↗
DOE OSTI2025

Microbead Encapsulation for Protection of Electronic Components

Here, this study investigates the application of microbeads as an innovative encapsulation technique to protect electronic components from harsh mechanical strain. Traditional encapsulation methods using hard epoxy provide substantial mechanical support but create thermal expansion mismatch issues, potentially leading to electronic component failure. We explore the use of finely powdered microbeads to achieve protective structures combining stiffness and energy absorption. The research focuses on key variables, including microbead size, microbead roughness, compaction of microbeads, and circuit board mounting in the encapsulation, all of which influence the encapsulation’s effectiveness. Experimental setups and testing protocols were developed to assess the performance of various microbead materials under different impact conditions. Results demonstrate that microbead encapsulation significantly reduces strain on circuit boards, minimizing the risk of damage during mechanical shocks. However, challenges remain, such as optimizing microbead characteristics and modeling their behavior within large-scale circuit board assemblies. Despite these challenges, the findings suggest that microbead encapsulation offers a promising alternative to conventional methods, enhancing the durability and reliability of electronic components in high-stress environments.

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