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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
DOE OSTI2019

UPC++ v1.0 Specification (Revision 2019.9.0)

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. We are revising the library under the auspices of the DOE’s Exascale Computing Project, to meet the needs of applications requiring PGAS support. UPC++ is intended for implementing elaborate distributed data structures where communication is irregular or fine-grained. The UPC++ interfaces for moving non-contiguous data and handling memories with different optimal access methods are composable and similar to those used in conventional C++. The UPC++ programmer can expect communication to run at close to hardware speeds. The key facilities in UPC++ are global pointers, that enable the programmer to express ownership information for improving locality, one-sided communication, both put/get and RPC, futures and continuations. Futures capture data readiness state, which is useful in making scheduling decisions, and continuations provide for completion handling via callbacks. Together, these enable the programmer to chain together a DAG of operations to execute asynchronously as high-latency dependencies become satisfied.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

UPC++ Specification v1.0, Draft 8

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. We are revising the library under the auspices of the DOE’s Exascale Computing Project, to meet the needs of applications requiring PGAS support. UPC++ is intended for implementing elaborate distributed data structures where communication is irregular or fine-grained. The UPC++ interfaces for moving non-contiguous data and handling memories with different optimal access methods are composable and similar to those used in conventional C++. The UPC++ programmer can expect communication to run at close to hardware speeds. The key facilities in UPC++ are global pointers, that enable the programmer to express ownership information for improving locality, one-sided communication, both put/get and RPC, futures and continuations. Futures capture data readiness state, which is useful in making scheduling decisions, and continuations provide for completion handling via callbacks. Together, these enable the programmer to chain together a DAG of operations to execute asynchronously as high-latency dependencies become satisfied.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems

Fail-slow hardware is an under-studied failure mode. We present a study of 114 reports of fail-slow hardware incidents, collected from large-scale cluster deployments in 14 institutions. We show that all hardware types such as disk, SSD, CPU, memory, and network components can exhibit performance faults. We made several important observations such as faults convert from one form to another, the cascading root causes and impacts can be long, and fail-slow faults can have varying symptoms. From this study, we make suggestions to vendors, operators, and systems designers.

fail-slow↗
DOE OSTI2022

Computer Science Research Needs for Parallel Discrete Event Simulation (PDES)

Historically, scientific computing efforts have demonstrated the clear need for, and effective use of, supercomputing with traditional time-stepped simulations. Nevertheless, there are several areas in the mission spaces of the U.S. Department of Energy and other agencies waiting to tap advanced computing research using a different, discrete event style of modeling, simulation, and analysis. These span a wide spectrum of applications including energy grid resilience, urban planning and policy, transportation science, building technologies, emergency response and planning, environmental impact analysis, computational epidemiology, Internet communications, cyber security, and cyber-physical systems, to name only a few. Even within traditional scientific applications, the role of discrete event modes of execution is increasing in the form of new event-based mathematical solvers such as quantized state integration methods and discrete-continuous hybrid system solvers. Co-design of advanced supercomputing hardware systems is another area that exploits discrete event simulation at its core for effective analyses. Complex systems, entity behaviors and interconnections play a significant role in all these applications, which are mapped to large-scale models with discrete event formulations. To make advancements in all the aforementioned scientific areas, many technical aspects need to be more thoroughly studied and deeply understood in parallel discrete event simulation (PDES). The unique dynamics inherent in a discrete event modeling approach, by their very nature, intersect and influence the entire stack of the computing system, including (a) the unique nature of the instruction sets exercised in PDES workloads without a predominance of high-precision floating point operations, (b) virtual time-constrained multi-threaded execution of many logical processes per processor, (c) extremely variable and difficult to predict network traffic characteristics, (d) interfaces and inter-dependencies with machine learning and artificial intelligence codes at higher software layers, and (e) highly challenging load balancing needs, especially in effectively accounting for accelerated/extremely heterogeneous computing in current and future high-performance computing systems. Efficient and accurate parallel execution of PDES workloads is also dominated by challenges in dealing with their asynchronous concurrency fundamentally present at the model level. Conservative synchronization, optimistic/speculative synchronization, and their hybrid schemes open new questions in fundamental computer science with respect to reversibility of computation and prediction (lookahead) of behaviors inherent within model codes. On the implementation front, there are relatively few scalable, general-purpose parallel discrete event simulators in the world, and even fewer have been studied on emerging hardware platforms. To enable scientific advances using PDES, the research needs in computer science must also be pursued and met in the intersection of the algorithmic and hardware-aware aspects of scalable PDES engines. This report is aimed at capturing a computer science-oriented view of this important area of research in PDES, presenting a sample of important applications with their inherent discrete event technology elements. Needs are outlined in core areas of parallel discrete event research as well as cross-cutting directions in computer science research that positively impact scientific advancements across several important application areas. A selection of priority research opportunities in advanced computing for PDES is identified to serve as reference for key research topics and their order of importance for scientific advancements.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Memristive Ion Channel-Doped Biomembranes as Synaptic Mimics

Solid-state neuromorphic systems based on transistors or memristors have yet to achieve the interconnectivity, performance, and energy efficiency of the brain due to excessive noise, undesirable material properties, and nonbiological switching mechanisms. Here in this work, we demonstrate that an alamethicin-doped, synthetic biomembrane exhibits memristive behavior, emulates key synaptic functions including paired-pulse facilitation and depression, and enables learning and computing. Unlike state-of-the-art devices, our two-terminal, biomolecular memristor features similar structure (biomembrane), switching mechanism (ion channels), and ionic transport modality as biological synapses while operating at considerably lower power. The reversible and volatile voltage-driven insertion of alamethicin peptides into an insulating lipid bilayer creates conductive pathways that exhibit pinched current–voltage hysteresis at potentials above their insertion threshold. Moreover, the synapse-like dynamic properties of the biomolecular memristor allow for simplified learning circuit implementations. Finally, low-power memristive devices based on stimuli-responsive biomolecules represent a major advance toward implementation of full synaptic functionality in neuromorphic hardware.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Use of Multiple Tracer Gases to Quantify Vane Trailing Edge Flow Into Turbine Rim Seals

Abstract Overlapping features are commonly used as rim seals between stationary and rotating components in a turbine stage. These rim seals are used to prevent main gas path ingestion to the wheelspace cavity, which reduces the lifespan of critical engine components such as the turbine disk. In addition to the overlapping features, purge flow, diverted from the compressor, is injected into the rim cavity to act as an airflow sealing mechanism. Previous research identified that in addition to the purge flow in the rim cavity, cooling flow from the vane trailing edge (VTE) is ingested into the rim seal cavity carrying the potential to cool components in the wheelspace. These previous findings, however, were not able to distinctly separate purge from VTE cooling flows, which is the contribution of this paper based on uniquely using two different tracer gases. A one-stage test turbine operating at engine-relevant conditions and consisting of real engine hardware was used to validate and quantify the ingestion of the VTE flow by independently seeding the purge and VTE flows with two different tracer gases. Experimental results show the presence of VTE flow in the rim seal throughout all purge flowrates evaluated. Circumferential variation of VTE flow was also studied both experimentally and computationally using a computational fluid dynamics model. Results showed that ingested VTE flow can reduce the detrimental effect of hot gas ingestion particularly at higher purge flowrates.

Engineering↗
DOE OSTI2017

RAJA Performance Suite

The RAJA Performance Suite is designed to evaluate performance of the RAJA performance portability library on a wide variety of important high performance computing (HPC) algorithmic lulmels. These kernels assess compiler optimizations and various parallel programming model backends accessible through RAJA, such as OpenMP, CUDA, etc. The Initial version of the suite contains 25 computational kernels, each of which appears in 6 variants: Baseline SequcntiaJ, RAJA SequentiaJ, Baseline OpenMP, RAJA OpenMP, Baseline CUDA, RAJA CUDA. All variants of each kernel perform essentially the same mathematical operations and the loop body code for each kernel is identical across all variants. There are a few kernels, such as those that contain reduction operations, that require CUDA-specific coding for their CUDA variants. ActuaJ computer instructions executed and how they run in parallel differs depending on the parallel programming model backend used and which optimizations are perfonned by the compiler used to build the Perfonnance Suite executable. The Suite will be used primarily by RAJA developers to perform regular assessments of RAJA performance across a range of hardware platforms and compilers as RAJA features are being developed. It will also be used by LLNL hardware and software vendor panners for new defining requirements for future computing platform procurements and acceptance testing. In particular, the RAJA Performance Suite will be used for compiler acceptance testing of the upcoming CORAUSierra machine {initial LLNL delivery expected in late-2017/early 2018) and the CORAL-2 procurement. The Suite will aJso be used to generate concise source code reproducers of compiler and runtime issues we uncover so that we may provide them to relevant vendors to be fixed.

Hornung, RichardD.↗
DOE OSTI2018

Deployable sensor system using mesh networking and satellite communication

A sensor system may be configured for continuous operation in a low resource environment and/or in extreme environmental conditions. The sensor system may have sufficient processing capabilities to provide scientific computing for pre-processing, quality control, statistical analysis, event classification, data compression and corrections (e.g., spikes in the data), autonomous decisions and actions, triggering other nodes, and information assurance functions that provide data confidentiality, data integrity, authentication, and non-repudiation. The hardware may have both mesh networking and satellite and cellular communication capability, and may be available for relatively low cost. Such a network provides the flexibility to have potentially any number of nodes be completely independent from one another. Thus, the network may scale across a diverse terrain.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Deployable sensor system using mesh networking and satellite communication

A sensor system may be configured for continuous operation in a low resource environment and/or in extreme environmental conditions. The sensor system may have sufficient processing capabilities to provide scientific computing for pre-processing, quality control, statistical analysis, event classification, data compression and corrections (e.g., spikes in the data), autonomous decisions and actions, triggering other nodes, and information assurance functions that provide data confidentiality, data integrity, authentication, and non-repudiation. The hardware may have both mesh networking and satellite and cellular communication capability, and may be available for relatively low cost. Such a network provides the flexibility to have potentially any number of nodes be completely independent from one another. Thus, the network may scale across a diverse terrain.

Frigo, Janette↗
DOE OSTI2023

Control Systems Design for STS Accelerator

The Second Target Station (STS) Project will expand the capabilities of the existing Spallation Neutron Source (SNS), with a suite of neutron instruments optimized for long wavelengths. A new accelerator transport line will be built to deliver one out of four SNS pulses to the new target station. The Integrated Control Systems (ICS) will provide remote control, monitoring, OPI, alarms, and archivers for the accelerator systems, such as magnets power supply, vacuum devices, and beam instrumentation. The ICS will upgrade the existing Linac LLRF controls to allow independent operation of the FTS and STS and support different power levels of the FTS and STS proton beam. The ICS accelerator controls are in the phase of preliminary design for the control systems of magnet power supply, vacuum, LLRF, Timing, Machine protection system (MPS), and computing and machine network. The accelerator control systems build upon the existing SNS Machine Control systems, use the SNS standard hardware and EPICS software, and take full advantage of the performance gains delivered by the PPU Project at SNS.

Yan, Jay↗
DOE OSTI2024

MFANS 2024 - Formally Proving Characteristics of Cyber-Physical Systems

Cyber-physical systems (CPS) are engineered systems that rely on the smooth integration of computational algorithms and physical elements. This integration presents new challenges for verifying that systems will behave as expected. The goal of this presentation is to present current challenges and potential solutions for the formal verification of cyber-physical systems. For cyber systems, formal methods refer to systematically rigorous mathematical techniques employed in the specification, development, analysis, and verification of both software and hardware systems. Recent advancements in computer science have yielded sophisticated tools specifically designed to address challenges associated with formal methods in complex systems. These tools leverage various foundational concepts such as logic, formal languages, program semantics, type systems, type theory, and automata theory. A notable achievement in the application of formal methods is the seL4 microkernel, claimed to be the first general-purpose operating-system kernel to be verified. Its proof implies the absence of bugs and guarantees that the kernel meets specifications. For physical systems, dynamic and control theory has a history of using rigorous analytic techniques to prove functional correctness. Lyapunov, optimal, classical, modern, and robust control theories all provide rigorous mathematical methods both to analyze system performance and to design controller that can be guaranteed to meet certain objectives. Recent computational techniques like level set theory and reachability analysis provide assertions that a system's state will avoid unsafe regions. Even though success has been independently achieved for cyber systems and physical systems, the integration of such systems creates new challenges. In particular, there is an obvious discrepancy between finite-state machines and infinite-state systems, resulting in different approaches for modeling and analyzing these system. While it is possible to simulate hybrid systems, this provides only a demonstration of a performance and not proof. For hybrid systems, current formal methods and system analysis approaches typically require a workarounds to work on hybrid systems like CPS. This paper will outline the state of the art and limits of current practice for formally verifying CPS and will identify possible research directions that require attention.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

UPC++ Specification v1.0, Draft 4

UPC++ is a C++11 library providing classes and functions that support Asynchronous Partitioned Global Address Space (APGAS) programming. We are revising the library under the auspices of the DOE’s Exascale Computing Project, to meet the needs of applications requiring PGAS support. UPC++ is intended for implementing elaborate distributed data structures where communication is irregular or fine-grained. The UPC++ interfaces for moving non-contiguous data and handling memories with different optimal access methods are composable and similar to those used in conventional C++. The UPC++ programmer can expect communication to run at close to hardware speeds. The key facilities in UPC++ are global pointers, that enable the programmer to express ownership information for improving locality, one-sided communication, both put/get and RPC, futures and continuations. Futures capture data readiness state, which is useful in making scheduling decisions, and continuations provide for completion handling via callbacks. Together, these enable the programmer to chain together a DAG of operations to execute asynchronously as high-latency dependencies become satisfied.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

UPC++ Specification v1.0, Draft 6

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. We are revising the library under the auspices of the DOE’s Exascale Computing Project, to meet the needs of applications requiring PGAS support. UPC++ is intended for implementing elaborate distributed data structures where communication is irregular or fine-grained. The UPC++ interfaces for moving non-contiguous data and handling memories with different optimal access methods are composable and similar to those used in conventional C++. The UPC++ programmer can expect communication to run at close to hardware speeds. The key facilities in UPC++ are global pointers, that enable the programmer to express ownership information for improving locality, one-sided communication, both put/get and RPC, futures and continuations. Futures capture data readiness state, which is useful in making scheduling decisions, and continuations provide for completion handling via callbacks. Together, these enable the programmer to chain together a DAG of operations to execute asynchronously as high-latency dependencies become satisfied.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Extreme ultraviolet microscope characterization using photomask surface roughness

We demonstrate a method for characterizing the field-dependent aberrations of a full-field synchrotron-based extreme ultraviolet microscope. The statistical uniformity of the inherent, atomic-scale roughness of readily-available photomask blanks enables a self-calibrating computational procedure using images acquired under standard operation. We characterize the aberrations across a 30-um field-of-view, demonstrating a minimum aberration magnitude of smaller than λ/21 rms averaged over the center 5-um area, with a measurement accuracy better than λ/180 rms. The measured field variation of aberrations is consistent with system geometry and agrees with prior characterizations of the same system. In certain cases, it may be possible to additionally recover the illumination wavefront from the same images. Our method is general and is easily applied to coherent imaging systems with steerable illumination without requiring invasive hardware or custom test objects; hence, it provides substantial benefits when characterizing microscopes and high-resolution imaging systems in situ.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Nuclear two point correlation functions on a quantum computer

The calculation of dynamic response functions is expected to be an early application benefiting from rapidly developing quantum hardware resources. The ability to calculate real-time quantities of strongly correlated quantum systems is one of the most exciting applications that can easily reach beyond the capabilities of traditional classical hardware. Response functions of fermionic systems at moderate momenta and energies corresponding roughly to the Fermi energy of the system are a potential early application because the relevant operators are nearly local, and the energies can be resolved in moderately short real time, reducing the spatial resolution and gate depth required. This is particularly the case in quasielastic electron and neutrino scattering from nuclei, a topic of great interest in the nuclear and particle physics communities and directly related to experiments designed to probe neutrino properties. In this paper we use current quantum hardware and error mitigation protocols to calculate response functions for a highly simplified nuclear model through calculations of a 2-point real time correlation function for a modified Fermi-Hubbard model in two dimensions with three distinguishable nucleons on four lattice sites.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2016

FatMan vs. LittleBoy: Scaling Up Linear Algebraic Operations in Scale-Out Data Platforms

Linear algebraic operations such as matrix manipulations form the kernel of many machine learning and other crucial algorithms. Scaling up as well as scaling out such algorithms are highly desirable to enable efficient processing over millions of data points. To this end, we present a matrix manipulation approach to effectively scale-up each node in a scale-out data parallel platform such as Apache Spark. Specifically, we enable hardware acceleration for matrix multiplications in a distributed Spark setup without user intervention. Our approach supports both dense and sparse distributed matrices, and provides flexible control of acceleration by matrix density. We demonstrate the benefit of our approach for generalized matrix multiplication operations over large matrices with up to four billion elements. To connect the effectiveness of our approach with machine learning applications, we performed Gramian matrix computation via generalized matrix multiplications. Our experiments show that our approach achieves more than 2× performance speed-up, and up to 96.1% computation improvement, compared to a state of the art Spark MLlib for dense matrices.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Performance Potential of Mixed Data Management Modes for Heterogeneous Memory Systems

Many high-performance systems now include different types of memory devices within the same compute platform to meet strict performance and cost constraints. Such heterogeneous memory systems often include an upper-level tier with better performance, but limited capacity, and lower-level tiers with higher capacity, but less bandwidth and longer latencies for reads and writes. To utilize the different memory layers efficiently, current systems rely on hardware-directed, memory -side caching or they provide facilities in the operating system (OS) that allow applications to make their own data-tier assignments. Since these data management options each come with their own set of trade-offs, many systems also include mixed data management configurations that allow applications to employ hardware- and software-directed management simultaneously, but for different portions of their address space. Despite the opportunity to address limitations of stand-alone data management options, such mixed management modes are under-utilized in practice, and have not been evaluated in prior studies of complex memory hardware. In this work, we develop custom program profiling, configurations, and policies to study the potential of mixed data management modes to outperform hardware- or software-based management schemes alone. Our experiments, conducted on an Intel ® Knights Landing platform with high-bandwidth memory, demonstrate that the mixed data management mode achieves the same or better performance than the best stand-alone option for five memory intensive benchmark applications (run separately and in isolation), resulting in an average speedup compared to the best stand-alone policy of over 10 %, on average.

Effler, Chad↗