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Results for “LOGIC CIRCUIT”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Gallium Arsenide Domino Circuit

Advantages include reduced power and high speed. Experimental gallium arsenide field-effect-transistor (FET) domino circuit replicated in large numbers for use in dynamic-logic systems. Name of circuit denotes mode of operation, which logic signals propagate from each stage to next when successive stages operated at slightly staggered clock cycles, in manner reminiscent of dominoes falling in a row. Building block of domino circuit includes input, inverter, and level-shifting substages. Combinational logic executed in input substage. During low half of clock cycle, result of logic operation transmitted to following stage.

Yang, Long↗
NASA NTRS1966

Digital system provides superregulation of nanosecond amplifier-discriminator circuit

Feedback system employing a digital logic comparator to detect and correct amplifier drift provides stable gain characteristics for nanosecond amplifiers used in counting applications. Additional anticoincidence logic enables application of the regulation circuit to the amplifier and discriminator while they are mounted in an operable circuit.

Forges, K. G.↗
NASA NTRS1965

5KW pulse width modulated static inverter

Design verification tests for logic and low level circuits, and preliminary single-phase breadboard of pulse width modulated static inverter

PULSE WIDTH MODULATION /PWM/↗
NASA NTRS1985

Processing of Image Data by Integrated Circuits

Sensors combined with logic and memory circuitry. Cross-correlation of two inputs accomplished by transversal filter. Position of image taken to point where image and template data yield maximum value correlation function. Circuit used for controlling robots, medical-image analysis, automatic vehicle guidance, and precise pointing of scientific cameras.

Armstrong, R. W.↗
DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
NASA NTRS1992

Bit-systolic arithmetic arrays using dynamic differential gallium arsenide circuits

A new family of gallium arsenide circuits for fine grained bit-systolic arithmetic arrays is introduced. This scheme combines features of two recent techniques of dynamic gallium arsenide FET logic and differential dynamic single-clock CMOS logic. The resulting circuits are fast and compact, with tightly constrained series FET propagation paths, low fanout, no dc power dissipation, and depletion FET implementation without level shifting diodes.

Beagles, Grant↗
NASA NTRS1975

High power ferrite microwave switch

A high power ferrite microwave switch was developed along with associated electronic driver circuits for operation in a spaceborne high power microwave transmitter in geostationary orbit. Three units were built and tested in a space environment to demonstrate conformance to the required performance characteristics. Each unit consisted of an input magic-tee hybrid, two non-reciprocal latching ferrite phase shifters, an out short-slot 3 db quadrature coupler, a dual driver electronic circuit, and input logic interface circuitry. The basic mode of operation of the high power ferrite microwave switch is identical to that of a four-port, differential phase shift, switchable circulator. By appropriately designing the phase shifters and electronic driver circuits to operate in the flux-transfer magnetization mode, power and temperature insensitive operation was achieved. A list of the realized characteristics of the developed units is given.

Bardash, I.↗
NASA NTRS2010

Precise delay measurement through combinatorial logic

A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

Burke, Gary R.↗
NASA NTRS2018

Using GPS Receiver 1PPS Output to Verify Time Stamp Accuracy and Measure Propagation Delay

A simple pulse overlay circuit using a logic OR gate was developed to overlay a precise leading edge 1 pulse per second time reference marker from a global positioning system receiver onto a non-return -to- zero-level pulse code modulation telemetry data stream to validate time stamp accuracy and measure propagation delay in telemetry equipment. A pulse overlay (PO) circuit was designed to produce a time reference marker within a pulse code modulation (PCM) telemetry data stream that was recorded and analyzed to validate an IRIG Standard 106-17 Chapter 10 recorder’s time stamp accuracy [1]. A manufacturer of a newly purchased Chapter 10 recorder claimed the time stamp accuracy to be better than 10 microseconds (μs) with only IRIG-B120 (IRIG-B) input and better than 1 μs with IRIG-B and one pulse per second (1PPS) inputs. The PO circuit and a Chapter 10 recorder test setup were used to verify the vendor’s data-time synchronization claims and to justify infrastructure upgrade costs to connect additional cables to each purchased recorder. The circuit was also used to measure the propagation delay (PD) of a long distance Telemetry multiplexer/demultiplexer telecommunication system which the manufacturer did not provide a PD specification. Using the one pulse per second time reference marker of the global positioning system receiver and the pulse overlay circuit to overlay the one pulse per second variable pulse width signal into a pulse code modulation telemetry stream provided an excellent means to validate time stamp accuracy within a Chapter 10 recorder and to measure propagation delays within a normal telemetry operating environment. The positive results from the Chapter 10 recorder tests validated the vendor’s claims and justified the implementation to add the one pulse per second signal to the range Chapter 10 recorders. The pulse overlay circuit and test setups defined in this paper can easily be used to measure other telemetry equipment.

Knudtson, Kevin↗
NASA NTRS1974

Digital transmitter for data bus communications system

Digital transmitter designed for Manchester coded signals (and all signals with ac waveforms) generated at a rate of one megabit per second includes efficient output isolation circuit. Transmitter consists of logic control section, amplifier, and output isolation section. Output isolation circuit provides dynamic impedance at terminals as function of amplifier output level.

Proch, G. E.↗
NASA NTRS1980

LSI logic for phase-control rectifiers

Signals for controlling phase-controlled rectifier circuit are generated by combinatorial logic than can be implemented in large-scale integration (LSI). LSI circuit saves space, weight, and assembly time compared to previous controls that employ one-shot multivibrators, latches, and capacitors. LSI logic functions by sensing three phases of ac power source and by comparing actual currents with intended currents.

Dolland, C.↗
DOE OSTI2024

A nanoscale photonic thermal transistor for sub-second heat flow switching

Abstract Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VO x )-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.

42 ENGINEERING↗
NASA NTRS1977

Changing NRZ data to biphase logic

Simple arrangement of four integrated circuits changes stream of binary data from non-return-to-zero (NRZ) coding to biphase logic coding. Selection of wiring and integrated circuits enables control and balancing of propagation delay without requiring excessive and expensive hardware.

Baker, E. B.↗
NASA NTRS1971

Television multiplexing system

System with single, standard, wideband line transmits ten or more real time TV video data displays over hard wire to recorders more than 22.5 km from source. Digital logic and integrated circuits ensure high reliability and low maintenance. System is adaptable for video sampling applications.

Simpkins, L. G.↗
NASA NTRS1971

Monolithic parallel processor, phase 1A

A four-bit parallel processor LSI array was designed and fabricated using COS/MOS integrated-circuit technology. The design features include the provision for interconnecting groups of parallel-processor chips to form an expanded processor of any desired word length. This 800-transistor "computer on a chip' circuit has the logic capability of a medium-size, medium-speed, general-purpose computer suitable for sophisticated scientific data processing. The ability to fabricate this device repetitively was demonstrated.

Source record↗
NASA NTRS1978

CMOS bulk-metal design handbook

User's guide describes techniques for generating precision mask artwork for complex CMOS integrated circuits, starting from logic diagram. Techniques are based on standard-cell approach. Guide also includes user guidelines for designing efficient CMOS arrays.

Edge, T. M.↗
NASA NTRS1981

CADAT network translator

Program converts cell-net data into logic-gate models for use in test and simulation programs. Input consists of either Place, Route, and Fold (PRF) or Place-and-Route-in-Two-Dimensions (PR2D) layout data deck. Output consists of either Test Pattern Generator (TPG) or Logic-Simulation (LOGSIM) logic circuitry data deck. Designer needs to build only logic-gate-model circuit description since program acts as translator. Language is FORTRAN IV.

Pitts, E. R.↗