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At least 271 records · Page 15

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NASA NTRS2007

Repair of Electronics for Long Duration Spaceflight

To reduce mission risk, long duration spaceflight and exploration activities will require greater degrees of self-sufficiency with regards to repair capability than have ever been employed before in space exploration. The current repair paradigm of replacing Orbital Replacement Units (ORUs) of malfunctioning avionics and electronic hardware will be impractical, since carrying all of the spares that could possibly be needed for a long duration mission would require upmass and volume at unprecedented and unacceptable levels. A strategy of component-level repair for electronics, however, could significantly reduce the mass and volume necessary for spares and enhance mission safety via a generic contingency capability. This approach is already used to varying degrees by the U.S. Navy, where vessels at sea experience some similar constraints such as the need for self sufficiency for moderately long time periods, and restrictions on volume of repair spares and infrastructure. The concept of conducting component-level repairs of electronics in spacecraft requires the development of design guidelines for future avionics (to enable repair), development of diagnostic techniques to allow an astronaut to pinpoint the faulty component aboard a vastly complex vehicle, and development of tools and methodologies for dealing with the physical processes of replacing the component. This physical process includes tasks such as conformal coating removal and replacement, component removal, replacement, and alignment--all in the difficulty of a reduced gravity environment. Further, the gravitational effects on the soldering process must be characterized and accounted for to ensure reliability of the newly repaired components. The Component-Level Electronics-Assembly Repair (CLEAR) project under the NASA Supportability program was established to develop and demonstrate the practicality of this repair approach. CLEAR involves collaborative efforts between NASA s Glenn Research Center, Langley Research Center, Johnson Space Center, the National Center for Space Exploration Research, and the U.S. Navy. The project goals are 1) develop and demonstrate a manually-operated electronics repair capability to be conducted in a spacecraft environment; and 2) develop guidelines for designs of electronics that facilitates component-level repair for future space exploration efforts. This multi-faceted program utilizes a cross-disciplinary approach to examine pre- and post-repair diagnostics, conformal coating removal and replacement, component soldering, and electronics design for supportability. These areas are investigated by a combination of trade studies, ground based testing, reduced gravity aircraft testing, and actual spaceflight testing on the International Space Station (ISS) in multiple experiments. This paper details the efforts of this program, with emphasis on early trade study results, ground-based efforts, and two upcoming ISS experiments.

Pettegrew, Richard D.↗

NASA NTRS1994

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Carson, John C.↗

NASA NTRS1983

Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Anthony, Thomas R.↗

NASA NTRS1985

Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process of this invention involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Anthony, Thomas R.↗

NASA NTRS2008

Electromagnetically Clean Solar Arrays

The term 'electromagnetically clean solar array' ('EMCSA') refers to a panel that contains a planar array of solar photovoltaic cells and that, in comparison with a functionally equivalent solar-array panel of a type heretofore used on spacecraft, (1) exhibits less electromagnetic interferences to and from other nearby electrical and electronic equipment and (2) can be manufactured at lower cost. The reduction of electromagnetic interferences is effected through a combination of (1) electrically conductive, electrically grounded shielding and (2) reduction of areas of current loops (in order to reduce magnetic moments). The reduction of cost is effected by designing the array to be fabricated as a more nearly unitary structure, using fewer components and fewer process steps. Although EMCSAs were conceived primarily for use on spacecraft they are also potentially advantageous for terrestrial applications in which there are requirements to limit electromagnetic interference. In a conventional solar panel of the type meant to be supplanted by an EMCSA panel, the wiring is normally located on the back side, separated from the cells, thereby giving rise to current loops having significant areas and, consequently, significant magnetic moments. Current-loop geometries are chosen in an effort to balance opposing magnetic moments to limit far-0field magnetic interactions, but the relatively large distances separating current loops makes full cancellation of magnetic fields problematic. The panel is assembled from bare photovoltaic cells by means of multiple sensitive process steps that contribute significantly to cost, especially if electomagnetic cleanliness is desired. The steps include applying a cover glass and electrical-interconnect-cell (CIC) sub-assemble, connecting the CIC subassemblies into strings of series-connected cells, laying down and adhesively bonding the strings onto a panel structure that has been made in a separate multi-step process, and mounting the wiring on the back of the panel. Each step increases the potential for occurrence of latent defects, loss of process control, and attrition of components. An EMCSA panel includes an integral cover made from a transparent material. The silicone cover supplants the individual cover glasses on the cells and serves as an additional unitary structural support that offers the advantage, relative to glass, of the robust, forgiving nature of the silcone material. The cover contains pockets that hold the solar cells in place during the lamination process. The cover is coated with indium tin oxide to make its surface electrically conductive, so that it serves as a contiguous, electrically grounded shield over the entire panel surface. The cells are mounted in proximity to metallic printed wiring. The painted-wiring layer comprises metal-film traces on a sheet of Kapton (or equivalent) polyimide. The traces include contact pads on one side of the sheet for interconnecting the cells. Return leads are on the opposite side of the sheet, positioned to form the return currents substantially as mirror images of, and in proximity to, the cell sheet currents, thereby minimizing magnetic moments. The printed-wiring arrangement mimics the back-wiring arrangement of conventional solar arrays, but the current-loop areas and the resulting magnetic moments are much smaller because the return-current paths are much closer to the solar-cell sheet currents. The contact pads are prepared with solder fo electrical and mechanical bonding to the cells. The pocketed cover/shield, the solar cells, the printed-wiring layer, an electrical bonding agent, a mechanical-bonding agent, a composite structural front-side face sheet, an aluminum honeycomb core, and a composite back-side face sheet are all assembled, then contact pads are soldered to the cells and the agents are cured in a single lamination process.

Stem, Theodore G.↗

NASA NTRS2009

Lunar Module Wiring Design Considerations and Failure Modes

This slide presentation reviews the considerations for the design of wiring for the Lunar Module. Included are a review of the choice of conductors and insulations, the wire splicing (i.e., crimping, and soldering), the wire connectors, and the fabrication of the wire harnesses. The problems in fabrication include the wires being the wrong length, the damage due to the sharp edges, the requried use of temproary protective covers and inadequate training. The problems in the wire harness installation include damge from sharp eges, work on adjacent harnesses, connector damage, and breaking wires. Engineering suggestions from the Apollo-era in reference to the conductors that are reviewed include: the use of plated conductors, and the use of alloys for stronger wiring. In refernce to insulation, the suggestions from Apollo era include the use of polymer tape-wrap wire insulation due to the light weight, however, other types of modern insulation might be more cost-effective. In reference to wire splices and terminal boards the suggestions from the Apollo Era include the use of crimp splices as superior to solder splices, joining multiple wire to a common point using modular plug-ins might be more reliable, but are heavier than crimp splicing. For connectors, the lessons from the Apollo era indicate that a rear environmental seal that does not require additional potting is preferred, and pins should be crimped or welded to the incoming wires and be removable from the rear of the connector.

Interbartolo, Michael↗

NASA NTRS2006

Neuro-Prosthetic Implants With Adjustable Electrode Arrays

Brushlike arrays of electrodes packaged with application-specific integrated circuits (ASICs) are undergoing development for use as electronic implants especially as neuro-prosthetic devices that might be implanted in brains to detect weak electrical signals generated by neurons. These implants partly resemble the ones reported in Integrated Electrode Arrays for Neuro-Prosthetic Implants (NPO-21198), NASA Tech Briefs, Vol. 27, No. 2 (February 2003), page 48. The basic idea underlying both the present and previously reported implants is that the electrodes would pick up signals from neurons and the ASICs would amplify and otherwise preprocess the signals for monitoring by external equipment. The figure presents a simplified and partly schematic view of an implant according to the present concept. Whereas the electrodes in an implant according to the previously reported concept would be microscopic wires, the electrodes according to the present concept are in the form of microscopic needles. An even more important difference would be that, unlike the previously reported concept, the present concept calls for the inclusion of microelectromechanical actuators for adjusting the depth of penetration of the electrodes into brain tissue. The prototype implant now under construction includes an array of 100 electrodes and corresponding array of electrode contact pads formed on opposite faces of a plate fabricated by techniques that are established in the art of microelectromechanical systems (MEMS). A mixed-signal ASIC under construction at the time of reporting the information for this article will include 100 analog amplifier channels (one amplifier per electrode). On one face of the mixed-signal ASIC there will be a solder-bump/micro-pad array that will have the same pitch as that of the electrode array, and that will be used to make the electrical and mechanical connections between the electrode array and the ASIC. Once the electrode array and the ASIC are soldered together, the remaining empty space between them will be filled with a biocompatible epoxy, the remaining exposed portions of the ASIC will be covered with micromachined plates for protection against corrosive bodily fluids, and then the ASIC and its covering micromachined plates will be coated with parylene

Whitacre, Jay↗

NASA NTRS2008

Column Grid Array Rework for High Reliability

Due to requirements for reduced size and weight, use of grid array packages in space applications has become common place. To meet the requirement of high reliability and high number of I/Os, ceramic column grid array packages (CCGA) were selected for major electronic components used in next MARS Rover mission (specifically high density Field Programmable Gate Arrays). ABSTRACT The probability of removal and replacement of these devices on the actual flight printed wiring board assemblies is deemed to be very high because of last minute discoveries in final test which will dictate changes in the firmware. The questions and challenges presented to the manufacturing organizations engaged in the production of high reliability electronic assemblies are, Is the reliability of the PWBA adversely affected by rework (removal and replacement) of the CGA package? and How many times can we rework the same board without destroying a pad or degrading the lifetime of the assembly? To answer these questions, the most complex printed wiring board assembly used by the project was chosen to be used as the test vehicle, the PWB was modified to provide a daisy chain pattern, and a number of bare PWB s were acquired to this modified design. Non-functional 624 pin CGA packages with internal daisy chained matching the pattern on the PWB were procured. The combination of the modified PWB and the daisy chained packages enables continuity measurements of every soldered contact during subsequent testing and thermal cycling. Several test vehicles boards were assembled, reworked and then thermal cycled to assess the reliability of the solder joints and board material including pads and traces near the CGA. The details of rework process and results of thermal cycling are presented in this paper.

high reliability↗

NASA NTRS2010

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗

NASA NTRS2010

Workmanship Standards Personnel Training and Certification Explained

This slide presentation reviews the standards that NASA requires for workmanship and discusses the rationale and the NASA-STD-8739.x standard series. The training and certification of inspectors and operators is to guarantee that workmanship is qualified for NASA applications. The NASA workmanship standard documents review the standards for: Polymeric Applications, Surface Mount Technology, Soldered Electrical Connections, Crimp, Cable and Harnesses, Fiber Optic Terminations, including ANSI and IPC standards for Electrostatic Discharge Safety, Space Applications Electronic Hardware and Requirements for Soldered Electrical and Electronic Assemblies. It also reviews the certification requirements for appropriate personnel. It also reviews the various levels of trainers for the various requirements. There is also a review of calibration requirements for training equipment. Some variations on the curriculum are allowed. NASA requires operators and inspectors to be certified by their employer to ensure that oversight is being performed.

Plante, Jeannette F.↗

NASA NTRS2003

Zipper Connectors for Flexible Electronic Circuits

Devices that look and function much like conventional zippers on clothing have been proposed as connectors for flexible electronic circuits. Heretofore, flexible electronic circuits have commonly included rigid connectors like those of conventional rigid electronic circuits. The proposed zipper connectors would make it possible to connect and disconnect flexible circuits quickly and easily. Moreover, the flexibility of zipper connectors would make them more (relative to rigid connectors) compatible with flexible circuits, so that the advantages of flexible circuitry could be realized more fully. Like a conventional zipper, a zipper according to the proposal would include teeth anchored on flexible tapes, a slider with a loosely attached clasp, a box at one end of the rows of mating teeth, and stops at the opposite ends. The tapes would be made of a plastic or other dielectric material. On each of the two mating sides of the zipper, metal teeth would alternate with dielectric (plastic) teeth, there being two metal teeth for each plastic one. When the zipper was closed, each metal tooth from one side would be in mechanical and electrical contact with a designated metal tooth from the other side, and these mating metal teeth would be electrically insulated from the next pair of mating metal teeth by an intervening plastic tooth. The metal teeth would be soldered or crimped to copper tabs. Wires or other conductors connected to electronic circuits would be soldered or crimped to the ends of the tabs opposite the teeth.

Barnes, Kevin N.↗

NASA NTRS2011

Optimization of Indium Bump Morphology for Improved Flip Chip Devices

Flip-chip hybridization, also known as bump bonding, is a packaging technique for microelectronic devices that directly connects an active element or detector to a substrate readout face-to-face, eliminating the need for wire bonding. In order to make conductive links between the two parts, a solder material is used between the bond pads on each side. Solder bumps, composed of indium metal, are typically deposited by thermal evaporation onto the active regions of the device and substrate. While indium bump technology has been a part of the electronic interconnect process field for many years and has been extensively employed in the infrared imager industry, obtaining a reliable, high-yield process for high-density patterns of bumps can be quite difficult. Under the right conditions, a moderate hydrogen plasma exposure can raise the temperature of the indium bump to the point where it can flow. This flow can result in a desirable shape where indium will efficiently wet the metal contact pad to provide good electrical contact to the underlying readout or imager circuit. However, it is extremely important to carefully control this process as the intensity of the hydrogen plasma treatment dramatically affects the indium bump morphology. To ensure the fine-tuning of this reflow process, it is necessary to have realtime feedback on the status of the bumps. With an appropriately placed viewport in a plasma chamber, one can image a small field (a square of approximately 5 millimeters on each side) of the bumps (10-20 microns in size) during the hydrogen plasma reflow process. By monitoring the shape of the bumps in real time using a video camera mounted to a telescoping 12 magnifying zoom lens and associated optical elements, an engineer can precisely determine when the reflow of the bumps has occurred, and can shut off the plasma before evaporation or de-wetting takes place.

Jones, Todd J.↗

NASA NTRS2012

Effect of Compressive Stresses on Leakage Currents in Microchip Tantalum Capacitors

Microchip tantalum capacitors are manufactured using new technologies that allow for production of small size capacitors (down to EIA case size 0402) with volumetric efficiency much greater than for regular chip capacitors. Due to a small size of the parts and leadless design they might be more sensitive to mechanical stresses that develop after soldering onto printed wiring boards (PWB) compared to standard chip capacitors. In this work, the effect of compressive stresses on leakage currents in capacitors has been investigated in the range of stresses up to 200 MPa. Significant, up to three orders of magnitude, variations of currents were observed after the stress exceeds a certain critical level that varied from 10 MPa to 180 MPa for capacitors used in this study. A stress-induced generation of electron traps in tantalum pentoxide dielectric is suggested to explain reversible variations of leakage currents in tantalum capacitors. Thermo-mechanical characteristics of microchip capacitors have been studied to estimate the level of stresses caused by assembly onto PWB and assess the risk of stress-related degradation and failures. Keywords: tantalum capacitors, leakage current, soldering, reliability, mechanical stress.

Teverovsky, Alexander↗

NASA NTRS2012

Focal Plane Alignment Utilizing Optical CMM

In many applications, an optical detector has to be located relative to mechanical reference points. One solution is to specify stringent requirements on (1) mounting the optical detector relative to the chip carrier, (2) soldering the chip carrier onto the printed circuit board (PCB), and (3) installing the PCB to the mechanical structure of the subsystem. Figure 1 shows a sketch of an optical detector mounted relative to mechanical reference with high positional accuracy. The optical detector is typically a fragile wafer that cannot be physically touched by any measurement tool. An optical coordinate measuring machine (CMM) can be used to position optical detectors relative to mechanical reference points. This approach will eliminate all requirements on positional tolerances. The only requirement is that the PCB is manufactured with oversized holes. An exaggerated sketch of this situation is shown in Figure 2. The sketch shows very loose tolerances on mounting the optical detector in the chip carrier, loose tolerance on soldering the chip carrier to the PCB, and finally large tolerance on where the mounting screws are located. The PCB is held with large screws and oversized holes. The PCB is mounted loosely so it can move freely around. The optical CMM measures the mechanical reference points. Based on these measurements, the required positions of the optical detector corners can be calculated. The optical CMM is commanded to go to the position where one detector corner is supposed to be. This is indicated with the cross-hairs in Figure 2(a). This figure is representative of the image of the optical CMM monitor. Using a suitable tapping tool, the PCB is manually tapped around until the corner of the optical detector is at the crosshairs of the optical CMM. The CMM is commanded to another corner, and the process is repeated a number of times until all corners of the optical detector are within a distance of 10 to 30 microns of the required position. The situation is sketched in Figure 2(b) (the figure also shows the tapping tool and where to tap). At this point the fasteners for the PCB are torqued slightly so the PCB can still move. The PCB location is adjusted again with the tapping tool. This process is repeated 3 to 4 times until the final torque is achieved. The oversized mounting holes are then filled with a liquid bonding agent to secure the board in position (not shown in the sketch). A 10- to 30-micron mounting accuracy has been achieved utilizing this method..

Liebe, Carl Christian↗

NASA NTRS2012

Sample Sealing Approaches for Mars Sample Return Caching

Objective ot this project was to investigate sealing methods for encapsulating samples in 1 cm diameter thin-walled sample tubes applicable to future proposed Mars Sample Return Techniques implemented include a spring energized Teflon sleeve plug, a crimped tube seal, a heat-activated shape memory alloy plug, a shape memory alloy activated cap, a solder-based plug, and a solder-based cap

Mars Sample Return (MSR) mission↗

NASA NTRS2013

Methods and apparatus for microwave tissue welding for wound closure

Methods and apparatus for joining biological tissue together are provided. In at least one specific embodiment, a method for joining biological tissue together can include applying a biological solder on a wound. A barrier layer can be disposed on the biological solder. An antenna can be located in proximate spatial relationship to the barrier layer. An impedance of the antenna can be matched to an impedance of the wound. Microwaves from a signal generator can be transmitted through the antenna to weld two or more biological tissue pieces of the wound together. A power of the microwaves can be adjusted by a control circuit disposed between the antenna and the signal generator. The heating profile within the tissue may be adjusted and controlled by the placement of metallic microspheres in or around the wound.

Arndt, G. Dickey↗

NASA NTRS2014

The Significance of Breakdown Voltages for Quality Assurance of Low-Voltage BME Ceramic Capacitors

Application of thin dielectric, base metal electrode (BME) ceramic capacitors for high-reliability applications requires development of testing procedures that can assure high quality and reliability of the parts. In this work, distributions of breakdown voltages (VBR) in variety of low-voltage BME multilayer ceramic capacitors (MLCCs) have been measured and analyzed. It has been shown that analysis of the distributions can indicate the proportion of defective parts in the lot and significance of the defects. Variations of the distributions after solder dip testing allow for an assessment of the robustness of capacitors to soldering-related stresses. The drawbacks of the existing screening and qualification methods to reveal defects in high-value, low-voltage MLCCs and the importance of VBR measurements are discussed. Analysis has shown that due to a larger concentration of oxygen vacancies, defect-related degradation of the insulation resistance (IR) and failures are more likely in BME compared to the precious metal electrode (PME) capacitors.

reliability↗

NASA NTRS2014

Reliability of CGA/LGA/HDI Package Board/Assembly (Final Report)

Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented.

Ghaffaroam. Reza↗