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At least 271 records · Page 15

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DOE OSTI2020

Revealing the Nano-Scale Structure and Properties of Pinholes in SiOx Layers for POLO Contacts

In this contribution, we report on the charge collection characteristics of silicon photovoltaic devices with passivated contacts based on the c-Si/SiOx /poly-Si structure. Using electron-beam induced current (EBIC) imaging in plan-view and cross-section orientations, we find that charge collection in a device with a 1.5-nm-thick SiOx layer is fairly uniform in the p-n junction region and does not appear to be influenced by pyramidal surface texture. In contrast, a device with a 2.2-nm-thick oxide layer shows significant spatial variation in the charge-collection signal. The locations where we observe preferential collection of excess carriers is very sensitive to the processing conditions used to grow and breakup the SiOx passivation layer. In some cases the apexes of the pyramids exhibit reduced EBIC signal as the valleys between adjacent pyramids show the strongest collection. Other conditions yield enhanced charge collection at well defined spots on pyramid faces with no observable collection in the valleys.

EBIC↗

DOE OSTI2026

Resilience of High-Efficiency CdSeTe:As and CdSeTe:Cu Solar Cells to Proton Irradiation

Power generation in space is currently dominated by expensive III-V multi-junction photovoltaic (PV) devices and cheap crystalline silicon (c-Si) PV devices. Both of these technologies degrade rapidly in proton-radiation-rich space environments, such as the Van Allen belt. The present study of cadmium selenide telluride- (CdSeTe-) based PV devices exposed to 150-to-1500 keV proton irradiation with fluences up to 9 x 1013 cm-2 reveal a more radiation-hard alternative to III-V and c-Si PV technologies. We report on measurement and analysis of current density vs voltage (JV), external quantum efficiency (EQE), external radiative efficiency, and capacitance vs voltage (CV) characteristics. JV characteristics of As-doped CdSeTe devices show 80% remaining power conversion efficiency (PCE) relative to unexposed controls when exposed to 650 keV protons at a fluence of 1012 cm-2. Under these same irradiation conditions, Cu-doped CdSeTe devices demonstrate an even better 95% PCE retention compared with unirradiated control devices. Evidence of radiation-induced absorber p-type doping compensation is observed in the glass-side EQE at 0 V and CV characteristics of most of the irradiated CdSeTe:As devices, but clear compensation is evident only for the most heavily irradiated CdSeTe:Cu devices. Elevated blue-green photocurrent in the film-side 0 V EQE suggests a buried junction in the most heavily irradiated CdSeTe:As devices. Although CdSeTe:Cu devices are the more resilient of the CdSeTe structures, both CdSeTe-based technologies are radiation-hard when compared to c-Si and III-V multi-junction PV.

14 SOLAR ENERGY↗

DOE OSTI2024

DC Microgrid Reliability Enhancement with Adaptive Converter Thermal Management

Due to the different device selections, aging levels, and thermal dissipation performance, some converters may take additional thermal stress on switching devices than others in paralleled converter systems, which will reduce system reliability. To address this problem, this paper proposes a power-sharing strategy with adaptive thermal management. First, the temperature-based power loss model and electrical-thermal model are established. Based on that, a high-accuracy IGBT junction temperature estimate considering the power loss-temperature coupling can be achieved. Further, the thermal-sharing for all the switching devices in paralleled converters can be achieved with the proposed adaptive thermal management strategy. The proposed strategy can change the power-sharing ratio adaptively according to the system operation conditions, which will contribute to the system reliability enhancement. The effectiveness of the proposed strategy is verified through PLECS thermal simulation and joint real-time simulation with Dspace and RT-box.

DC microgrid↗

NASA NTRS1975

V-grooved silicon solar cells

Silicon solar cells with macroscopic V-shaped grooves and microscopically texturized surfaces were made by preferential etching techniques. Various conditions for potassium hydroxide and hydrazine hydrate etching were investigated. Optical reflection losses from these surface were reduced. The reduced reflection occurred at all wavelengths and resulted in improved short circuit current and spectral response. Improved collection efficiency is also expected from this structure due to generation of carriers closer to the cell junction. Microscopic point measurements of collected current using a scanning electron microscope showed that current collected at the peaks of the texturized surface were only 80 percent of those collected in the valleys.

Baraona, C. R.↗

NASA NTRS1975

V-grooved silicon solar cells

Silicon solar cells with macroscopic V-shaped grooves and microscopically texturized surfaces have been made by preferential etching techniques. Various conditions for potassium hydroxide and hydrazine hydrate etching were investigated. Optical reflection losses from these surface were reduced. The reduced reflection occurred at all wavelengths and resulted in improved short circuit current and spectral response. Improved collection efficiency is also expected from this structure due to generation of carriers closer to the cell junction. Microscopic point measurements of collected current using a scanning electron microscope showed that current collected at the peaks of the texturized surface were only 80% of those collected in the valleys.

Baraona, C. R.↗

NASA NTRS1982

Grown-in defects and defects produced by 1-Me electron irradiated in Al0.3Ga0.7As P-N junction solar cells

Studies of grown-in defects and defects produced by the one-MeV electron irradiation in Al sub 0.3 Ga sub 0.7As p-n junction solar cells fabricated by liquid phase epitaxial (LPE) technique were made for the unirradiated and one-MeV electron irradiated samples, using DLTS and C-V methods. Defect and recombination parameters such as energy level, defect density, carrier capture cross sections and lifetimes were determined for various growth, annealing, and irradiation conditions.

Li, S. S.↗

NASA NTRS2001

Integrated Power Source Grant

Traditional spacecraft power systems incorporate a solar array energy source, an energy storage element (battery), and battery charge control and bus voltage regulation electronics to provide continuous electrical power for spacecraft systems and instruments. Dedicated power conditioning components provide limited fault isolation between systems and instruments, while a centralized power-switching unit provides spacecraft load control. Battery undervoltage conditions are detected by the spacecraft processor, which removes fault conditions and non-critical loads before permanent battery damage can occur. Cost effective operation of a micro-sat constellation requires a fault tolerant spacecraft architecture that minimizes on-orbit operational costs by permitting autonomous reconfiguration in response to unexpected fault conditions. A new micro-sat power system architecture that enhances spacecraft fault tolerance and improves power system survivability by continuously managing the battery charge and discharge processes on a cell-by-cell basis has been developed. This architecture is based on the Integrated Power Source (US patent 5644207), which integrates dual junction solar cells, Lithium Ion battery cells, and processor based charge control electronics into a structural panel that can be deployed or used to form a portion of the outer shell of a micro-spacecraft. The first generation Integrated Power Source is configured as a one inch thick panel in which prismatic Lithium Ion battery cells are arranged in a 3x7 matrix (26VDC) and a 3x1 matrix (3.7VDC) to provide the required output voltages and load currents. A multi-layer structure holds the battery cells, as well as the thermal insulators that are necessary to protect the Lithium Ion battery cells from the extreme temperatures of the solar cell layer. Independent thermal radiators, located on the back of the panel, are dedicated to the solar cell array, the electronics, and the battery cell array. In deployed panel applications, these radiators maintain the battery cells in an appropriate operational temperature range.

Source record↗

NASA NTRS2007

Preliminary Low Temperature Electron Irradiation of Triple Junction Solar Cells

For many years extending solar power missions far from the sun has been a challenge not only due to the rapid falloff in solar intensity (intensity varies as inverse square of solar distance) but also because some of the solar cells in an array may exhibit a LILT (low intensity low temperature) degradation that reduces array performance. Recent LILT tests performed on commercial triple junction solar cells have shown that high performance can be obtained at solar distances as great as approx. 5 AU1. As a result, their use for missions going far from the sun has become very attractive. One additional question that remains is whether the radiation damage experienced by solar cells under low temperature conditions will be more severe than when measured during room temperature radiation tests where thermal annealing may take place. This is especially pertinent to missions such as the New Frontiers mission Juno, which will experience cell irradiation from the trapped electron environment at Jupiter. Recent testing2 has shown that low temperature proton irradiation (10 MeV) produces cell degradation results similar to room temperature irradiations and that thermal annealing does not play a factor. Although it is suggestive to propose the same would be observed for low temperature electron irradiations, this has not been verified. JPL has routinely performed radiation testing on commercial solar cells and has also performed LILT testing to characterize cell performance under far sun operating conditions. This research activity was intended to combine the features of both capabilities to investigate the possibility of any room temperature annealing that might influence the measured radiation damage. Although it was not possible to maintain the test cells at a constant low temperature between irradiation and electrical measurements, it was possible to obtain measurements with the cell temperature kept well below room temperature. A fluence of 1E15 1MeV electrons was selected as representative of a moderately high dose that might be expected for a solar powered mission. Fluences much greater than this would require large increases in array area and mass, compromising the ability of PV to compete with non-solar alternatives.

Stella, Paul M.↗

NASA NTRS1985

High-temperature thermocouple and heat flux gauge using a unique thin film-hardware hot junction

A special thin film-hardware material thermocouple (TC) and heat flux gauge concept for a reasonably high temperature and high flux flat plate heat transfer experiment was fabricated and tested to gauge temperatures of 911 K. This concept was developed for minimal disturbance of boundary layer temperature and flow over the plates and minimal disturbance of heat flux through the plates. Comparison of special heat flux gauge Stanton number output at steady-state conditions with benchmark literature data was good and agreement was within a calculated uncertainty of the measurement system. Also, good agreement of special TC and standard TC outputs was obtained and the results are encouraging. Oxidation of thin film thermoelements was a primary failure mode after about 5 of operation.

Liebert, C. H.↗

DOE OSTI2023

Role of grain boundary crystallography on void growth in FCC metals

The growth of an isolated spherical void at and near a grain boundary or a triple junction is studied by means of full-field crystal plasticity simulations with explicit representation of the void. To examine the fundamental aspects of void/grain boundary interactions in these cases, a three-dimensional large-strain elasto-viscoplastic fast-Fourier transform (LS-EVP-FFT) model with axisymmetric tensile periodic boundary conditions was developed. We employ this model to reveal the role of crystallography (grain orientations, grain boundary misorientation and inclination angle with respect to the largest component of the applied stress) and type of loading on void growth. It was found that grain orientation was the primary crystallographic feature governing void growth in strain-rate controlled simulations. For strains small enough to not significantly alter the local geometry, the overall growth of the void in bicrystal boundaries was not strongly affected by grain boundary inclination angle. The relative amount of void growth experienced within each grain in a bicrystal or tri-crystal was strongly dependent on the grain boundary inclination angle. We found a subset of orientations that exhibit faster void growth in bicrystal boundaries than inside the constituent single crystals. Last, we show that when placed primarily in one grain but near the grain boundary, void growth was similar to void growth when placed at the grain boundary. Furthermore, the growing void remained in the original grain and did not grow into the other grain, regardless of crystallographic character.

36 MATERIALS SCIENCE↗

DOE OSTI2020

Novel animal model of multiple sclerosis: The glial connexin gap junction as an environmental tuner for neuroinflammation

Abstract Connexins, which comprise gap junctions (GJs) via homotypic/heterotypic oligomerization, act as channels to connect opposing cells, mainly in solid organs such as the skin, liver, heart, and central/peripheral nervous system. Connexins are synthesized in the endoplasmic reticulum, assembled in the Golgi apparatus as hexamers, and inserted into the cell membrane as hemichannels. These hemichannels are closed under normal conditions until they combine to form clusters and connect to neighboring cells via GJs in a head‐to‐head configuration. Opening of hemichannels, which depends on the intra‐ or extracellular environment, allows various bioactive molecules to enter into or be released from the host cells. Recent pathological studies on human demyelinating diseases have revealed alterations of connexin expression patterns in demyelinating lesions. To elucidate the molecular mechanisms of connexins in the pathomechanisms of inflammatory demyelination, we induced experimental autoimmune encephalomyelitis (EAE) in connexin 30 (Cx30)‐deficient mice, oligodendroglia‐specific Cx47‐ablated mice, and astroglia‐specific Cx43‐ablated mice. We found that both astroglial‐Cx30‐deficient mice and Cx43‐ablated mice showed amelioration of the clinical course of EAE, while oligodendroglial‐Cx47‐ablated mice showed aggravation. These findings indicate the distinct role of connexins expressed in different cell types and the substantial contribution of connexin‐mediated pathology to demyelinating disorders. The imbalance in connexin expression, which is caused by the inflammatory environment, results in an increase in hemichannels in glial cells. The release of proinflammatory molecules induced by the increase in hemichannels on activated glial cells is a crucial mechanism of demyelinating disorders.

Yamasaki, Ryo↗

NASA NTRS2000

Power Systems Evaluated for Solar Electric Propulsion Vehicles

Solar electric propulsion (SEP) mission architectures are applicable to a wide range NASA missions including the robotic exploration of the outer planets in the next decade and the human exploration of Mars within the next 2 decades. SEP enables architectures that are very mass efficient with reasonable power levels (1-MW class) aerobrake and cryogenic upper-stage transportation technologies are utilized. In this architecture, the efficient SEP stage transfers the payload from low Earth orbit (LEO) High Energy Elliptical Parking Orbit (HEEPO) within a period of 6 to 12 months. highthrust, cryogenic upper stage and payload then separate from the SEP vehicle for injection to the planetary target, allowing for fast heliocentric trip times. This mission architecture offers a potential reduction in mass to LEO in comparison to alternative all-chemical nuclear propulsion schemes. Mass reductions may allow launch vehicle downsizing enable missions that would have been grounded because of cost constraints. The preceding figure illustrates a conceptual SEP stage design for a human Mars mission. Researchers at the NASA Glenn Research Center at Lewis Field designed conceptual SEP vehicle, conceived the mission architecture to use this vehicle, and analyzed the vehicle s performance. This SEP stage has a dry mass of 35 metric tons (MT), 40 MT of xenon propellant, and a photovoltaic array that spans 110 m, providing power to a cluster of eight 100-kW Hall thrusters. The stage can transfer an 80-MT payload and upper stage to the desired HEEPO. Preliminary packaging studies show this space-station-class SEP vehicle meets the proposed "Magnum" launch vehicle and volume requirements with considerable margin. An SEP vehicle for outer planetary missions, such as the Europa Mapper Mission, would be dramatically smaller than human Mars mission SEP stage. In this mission architecture, the SEP power system with the payload to provide spacecraft power throughout the mission. Several photovoltaic array design concepts were considered for the SEP vehicle power system for the human mission to Mars. These include a space station derivative, a SCARLET (Solar Concentrator Arrays with Refractive Linear Element Technology) derivative, and a hybrid inflatable-deployable thin polymer membrane array with thin-film solar cells (as shown in the concept illustration). This concept is based on a design developed for the Next Generation Space Telescope Sun shield. The array is divided into 16 independent electrical sections with 500-V, negative-grounded solar cell strings. The power system employs a channelized, 500-Vdc power management and distribution (PMAD) architecture with lithium ion batteries for energy storage for vehicle and payload secondary loads (the high-power Hall thrusters do not operate in eclipse periods). The 500-V PMAD voltage permits "direct-drive" thruster operation, greatly reducing the power processing unit size, complexity, and power loss. Similar power system architecture, designs, and technology are assumed for the Europa Mapper Mission SEP vehicle. The primary exceptions are that the photovoltaic array is assumed to consist of two rectangular wings and that the power system rating is 15 kW in Earth orbit and 200 W at Europa. To size the SEP vehicle power system, a dedicated Fortran code was developed to predict detailed power system performance, mass, and thermal control requirements. This code also modeled all the relevant Earth orbit environments; that is, the particulate radiation, plasma, meteoroids and debris, ultraviolet radiation, contamination, and thermal conditions. Analysis results for the Human Mars Mission SEP vehicle show a power system mass of 9-MT and photovoltaic array area of 5800-square meters for the thin-membrane design concept with CuInS2 thin-film cells. Power processing unit input power for a thin-membrane array design with three-junction, amorphous SiGe solar cells is shown in the graph. Power falls off rapidly inhe first weeks of the mission because of light-induced (Staebler-Wronksi) solar cell losses. During the next 200 days, power decreases steadily as the SEP stage spirals through the proton belts and sustains the bulk of the mission radiation damage. Once the vehicle apogee is above approximately four Earth radii, little additional degradation is incurred. From 400 to 800 days, a 1100-km "parking" orbit is maintained to await the next payload transfer opportunity. This orbit is below the main proton belt, and thus, little radiation dose is accumulated during this time period. During the second LEO-to-HEEPO transfer, power degrades somewhat further, but power requirements are still met. In comparison, the Europa Mapper SEP vehicle power system had a mass of 150 kg and a thin membrane array area of 100 square meters.

Kerslake, Thomas W.↗

NASA NTRS2006

Junction-to-Case Thermal Resistance of a Silicon Carbide Bipolar Junction Transistor Measured

Junction temperature of a prototype SiC-based bipolar junction transistor (BJT) was estimated by using the base-emitter voltage (V(sub BE)) characteristic for thermometry. The V(sub BE) was measured as a function of the base current (I(sub B)) at selected temperatures (T), all at a fixed collector current (I(sub C)) and under very low duty cycle pulse conditions. Under such conditions, the average temperature of the chip was taken to be the same as that of the temperature-controlled case. At increased duty cycle such as to substantially heat the chip, but same I(sub C) pulse height, the chip temperature was identified by matching the V(sub BE) to the thermometry curves. From the measured average power, the chip-to-case thermal resistance could be estimated, giving a reasonable value. A tentative explanation for an observed bunching with increasing temperature of the calibration curves may relate to an increasing dopant atom ionization. A first-cut analysis, however, does not support this.

Niedra, Janis M.↗

NASA NTRS2009

Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing it to a total of 12 cycles between -195 C and +250 C. Following the cycling activity, measurements were performed again at the test temperatures of -195 C, +21 C, and +250 C.

Patterson, Richard↗

DOE OSTI2026

Review on Perovskite Solar Cells: From Single‐Junction Devices to Tandem Deployment in Space

Perovskite solar cells (PSCs) have emerged as a transformative photovoltaic technology, offering high power conversion efficiency (PCE) and the potential for cost-effective manufacturing. However, stability and large-scale manufacturing remain critical challenges that must be addressed for widespread adoption. This review provides a roadmap from single-junction perovskite solar cells to tandem deployment in space. First, material-level innovations are discussed, including mixed-cation and low-dimensional perovskites, transport materials, and additives that improve thermal and structural stability while enhancing efficiency. Then, we examine both established industrial standards and emerging scientific protocols aimed at stabilizing PSCs under operational conditions, including tandem cell integration strategies and encapsulation techniques to mitigate performance degradation. Manufacturing scalability is a focal point, where deposition methods and green solvents are explored to improve large-area film uniformity and reduce environmental impact. Additionally, the increasing viability of PSCs in extraterrestrial environments is assessed, with emphasis on their performance in space applications, radiation resistance, and flexible lamination methods for deployment in extreme conditions. Progress across materials innovation, device architectures, stability testing protocols, and both terrestrial and extraterrestrial applications collectively drives perovskite photovoltaics toward higher efficiency, stability, and cost-effectiveness.

flexible PSCs↗

DOE OSTI2022

Thermal Optimization of a Silicon Carbide, Half-Bridge Power Module

This project describes the modeling process to design the packaging and heat exchanger for a half-bridge wide-bandgap (WBG) power semiconductor module. The module uses two silicon carbide, metal-oxide-semiconductor field-effect transistor (MOSFET) devices per switch position that are soldered to an aluminum nitride, direct-bond copper (DBC) substrate. A baseplate cooling configuration (e.g., no thermal grease) is used along with a water-ethylene glycol, jet-impingement-style heat exchanger. The heat exchanger was designed to be fabricated using prototyping equipment from the National Renewable Energy Laboratory, complies with automotive standards (for minimal channel sizes, flow rates, and coolant), and considers reliability aspects (i.e., erosion/corrosion). Device-scale computational fluid dynamics (CFD) is used first to design the slot jet impingement cooling configuration and compute the effective heat transfer coefficient (HTC) of the concept. The computed HTCs are then used as boundary conditions for a finite element study to optimize the package geometry (e.g., device layout and baseplate thickness) to minimize thermal resistance and minimize temperature variation between the module's four devices. Finally, a fluid manifold is designed to generate the slot jets and cool the devices. Module-scale CFD predicts a relatively low junction-to-fluid thermal resistance of 16.7 mm2 K/W, a 1.4 degrees C temperature variation between devices, and a total pressure drop of 5,860 Pa (0.85 psi) for the design. The thermal resistance of the module design is about 67% lower than the 2015 BMW i3 power electronics/modules thermal resistance.

DIRECT ENERGY CONVERSION↗

NASA NTRS2005

Making AlN(x) Tunnel Barriers Using a Low-Energy Nitrogen-Ion Beam

A technique based on accelerating positive nitrogen ions onto an aluminum layer has been demonstrated to be effective in forming thin (<2 nm thick) layers of aluminum nitride (AlN(x)) for use as tunnel barriers in Nb/Al-AlN(x)/Nb superconductor/insulator/ superconductor (SIS) Josephson junctions. AlN(x) is the present material of choice for tunnel barriers because, to a degree greater than that of any other suitable material, it offers the required combination of low leakage current at high current density and greater thermal stability. While ultra-thin AlN films with good thickness and stoichiometry control are easily formed using techniques such as reactive molecular beam epitaxy and chemical vapor deposition, growth temperatures of 900 C are necessary for the dissociative adsorption of nitrogen from either nitrogen (N2) or ammonia (NH3). These growth temperatures are prohibitively high for the formation of tunnel barriers on Nb films because interfacial reactions at temperatures as low as 200 to 300 C degrade device properties. Heretofore, deposition by reactive sputtering and nitridation of thin Al layers with DC and RF nitrogen plasmas have been successfully used to form AlN barriers in SIS junctions. However, precise control over critical current density Jc has proven to be a challenge, as is attaining adequate process reproducibility from system to system. The present ion-beam technique is an alternative to the plasma or reactive sputtering techniques as it provides a highly controlled arrival of reactive species, independent of the electrical conditions of the substrate or vacuum chamber. Independent and accurate control of parameters such as ion energy, flux, species, and direction promises more precise control of film characteristics such as stoichiometry and thickness than is the case with typical plasma processes. In particular, the background pressure during ion-beam nitride growth is 2 or 3 orders of magnitude lower, minimizing the formation of compounds with contaminants, which is critical in devices the performance of which is dictated by interfacial characteristics. In addition, the flux of incoming species can be measured in situ using ion probes so that the dose can be controlled accurately. The apparatus used in the present ion-beam technique includes a vacuum chamber containing a commercial collimated- ion-beam source, a supply of nitrogen and argon, and an ion probe for measuring the ion dose. Either argon or nitrogen can be used as the feed gases for the ion source, depending on whether cleaning of the substrate or growth of the nitride, respectively, is desired. Once the Nb base electrode and Al proximity layer have been deposited, the N2 gas line to the ion beam is vented and purged, and the ion-source is turned on until a stable discharge is obtained. The substrate is moved over the ion-beam source to expose the Al surface layer to the ion beam (see figure) for a specified duration for the formation of the nitride tunnel barrier. Next, the Nb counter-electrode layer is deposited on the nitride surface layer. The Nb/Al- AlN(x)/Nb-trilayer-covered substrate is then patterned into individual devices by use of conventional integrated-circuit processing techniques.

Kaul, Anupama↗

NASA NTRS2015

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

JFET↗