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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

The ePix10k 2-megapixel hard X-ray detector at LCLS

The ePix10ka2M (ePix10k) is a new large area detector specifically developed for X-ray free-electron laser (XFEL) applications. The hybrid pixel detector was developed at SLAC to provide a hard X-ray area detector with a high dynamic range, running at the 120 Hz repetition rate of the Linac Coherent Light Source (LCLS). The ePix10k consists of 16 modules, each with 352 × 384 pixels of 100 µm × 100 µm distributed on four ASICs, resulting in a 2.16 megapixel detector, with a 16.5 cm × 16.5 cm active area and ∼80% coverage. The high dynamic range is achieved with three distinct gain settings (low, medium, high) as well as two auto-ranging modes (high-to-low and medium-to-low). Here the three fixed gain modes are evaluated. The resulting dynamic range (from single photon counting to 10000 photons pixel −1 pulse −1 at 8 keV) makes it suitable for a large number of different XFEL experiments. The ePix10k replaces the large CSPAD in operation since 2011. The dimensions of the two detectors are similar, making the upgrade from CSPAD to ePix10k straightforward for most setups, with the ePix10k improving on experimental performance. The SLAC-developed ePix cameras all utilize a similar platform, are tailored to target different experimental conditions and are designed to provide an upgrade path for future high-repetition-rate XFELs. Here the first measurements on this new ePix10k detector are presented and the performance under typical XFEL conditions evaluated during an LCLS X-ray diffuse scattering experiment measuring the 9.5 keV X-ray photons scattered from a thin liquid jet.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Fast digital lossy compression for X-ray ptychographic data

Increases in X-ray brightness from synchrotron light sources lead to a requirement for higher frame rates from hybrid pixel array detectors (HPADs), while also favoring charge integration over photon counting. However, transfer of the full uncompressed data will begin to constrain detector design, as well as limit the achievable continuous frame rate. Here a data compression scheme that is easy to implement in a HPAD's application-specific integrated circuit (ASIC) is described, and how different degrees of compression affect image quality in ptychography, a commonly employed coherent imaging method, is examined. Using adaptive encoding quantization, it is shown in simulations that one can digitize signals up to 16383 photons per pixel (corresponding to 14 bits of information) using only 8 or 9 bits for data transfer, with negligible effect on the reconstructed image.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2026

Gaia: segmented germanium detector for high-energy X-ray fluorescence and spectroscopic imaging

We present Gaia, a monolithic array of 96 high-purity germanium pixel detectors integrated with a custom low-noise application-specific integrated circuit (ASIC) and a field-programmable gate array (FPGA)-based data acquisition system. The sensor operates at ∼100 K using a commercial closed-cycle cryocooler, with the in-vacuum electronics thermally isolated from the cold finger to ensure thermal stability. The system demonstrates an average energy resolution of 711 eV at 122 keV, measured using a 57 Co source, and 253 eV at 5.89 keV, measured with 55 Fe across all channels. The readout architecture incorporates a high-performance FPGA paired with a dual-core ARM processor, forming a complete embedded Linux-based computing platform. Communication between the processor and FPGA is handled via memory-mapped I/O, and data are streamed over high-speed gigabit Ethernet. A full-scale 384-pixel Gaia detector, based on this 96-element module, is currently under fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
DOE OSTI2020

Invited: Software defined accelerators from learning tools environment

Next generation systems, such as edge devices, will need to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. In this paper we present the Software Defined Accelerators From Learning Tools Environment (SODALITE), an automated open source high-level ML framework-to-verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets. The SODALITE approach will implement optimal designs by seamlessly combining custom components generated through high-level synthesis (HLS) with templated and fully tunable Intellectural Properties (IPs) and macros, integrated in an extendable resource library. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimensions.

High-Level Synthesis, Accelerators, Hardware-Softw↗
DOE OSTI2022

DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit data streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across application kernels. However, emerging streaming applications at the edge (scientific instruments, sensor networks, network processing) perform much more than digital signal processing and often are data and input dependent. This leads to extremely variable kernel execution times, severely impacting the throughput of the entire pipeline if resources are only statically allocated. Therefore, in this paper, we propose DRIPS — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We present a unified compiler framework to facilitate the mapping of a given streaming application onto the DRIPS CGRA architecture. The experimental results show that DRIPS achieves an average throughput improvement of 1.46$\times$ across a set of representative applications over a statically partitioned solution. The additional area overhead to enable dynamic rebalancing consumes 16.34% of the entire area for a 5x5 CGRA prototype.

Tan, Cheng↗
DOE OSTI2021

DynPaC: Coarse-Grained, Dynamic, and Partially Reconfigurable Array for Streaming Applications

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across kernels. However, streaming applications often are data-dependent, leading to variable kernel execution times depending on the input data and impacting the throughput of the entire pipeline if resources are statically allocated. Therefore, in this paper, we discuss the design of DynPaC — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We discuss the required software and hardware components to manage partial dynamic reconfiguration. We demonstrate that by supporting partial dynamic reconfiguration, we can obtain an average speedup of 1.44X for a representative set of applications w.r.t. static partitioning, with a limited area overhead (6.4% of the entire chip).

Tan, Cheng↗
DOE OSTI2021

Time-stamping and counting of single photons using fast camera

I will discuss fast optical cameras based on the back-illuminated silicon sensor and Timepix3 ASIC. The sensor has high quantum efficiency, and the chip provides nanosecond scale time resolution and data-driven readout with 80Mpix/sec bandwidth. The intensified version of the camera is single photon sensitive and since recently has been used for registration of single photons in a variety of quantum information science and quantum imaging experiments as well as for other applications. We briefly review the camera and describe recent experiments with a Hong-Ou-Mandel interferometer to characterize its photon counting capabilities.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2025

A Ce-Doped LiI Scintillator Film-Based High Rate, High Spatial Resolution Neutron Anger Camera for Neutron Scattering Facilities

The 2-D position sensitive neutron detectors featuring a significantly improved count rate capacity and a sub-mm spatial resolution are in high demand by neutron scattering facilities, especially the next generation high-flux spallation neutron sources (SNSs). They are anticipated to play a crucial role in fully utilizing the unprecedentedly high neutron brightness offered by these sources. In this work, a high rate and high spatial resolution neutron Anger camera has been successfully developed based on a Ce-doped microcolumnar LiI scintillator film and the PETsys TOFPET2 ASIC readout electronics. The performance evaluation was conducted in a standard laboratory environment as well as the High Flux Isotope Reactor (HFIR) at Oak Ridge National Laboratory (ORNL) with regard to light yield, γ-ray sensitivity, neutron detection efficiency, count rate capability, spatial resolution, and position linearity. The LiI:Ce scintillator was found to have a higher light yield and a lower γ-ray sensitivity than GS20 (i.e., 11729 versus 6000 photons/n and 1.67 × 10 −5 versus on the order of 10 −4 ). The neutron detection efficiency was measured to be 63% at 4.2 Å. This camera demonstrated an exceptional count rate capability, up to at least 481 kHz without rate loss. The spatial resolution was as good as 0.47 mm. Here, the position linearity was also enhanced.

High rate↗
DOE OSTI2020

Programming Strategies for Irregular Algorithms on the Emu Chick

The Emu Chick prototype implements migratory memory-side processing in a novel hardware system. Rather than transferring large amounts of data across the system interconnect, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each remote memory read. Previous work has characterized the performance of the Chick prototype in terms of memory bandwidth and programming differences from more typical, non-migratory platforms, but there has not yet been an analysis of algorithms on this system. This work evaluates irregular algorithms that could benefit from the lightweight, memory-side processing of the Chick and demonstrates techniques and optimization strategies for achieving performance in sparse matrix-vector multiply operation (SpMV), breadth-first search (BFS), and graph alignment across up to eight distributed nodes encompassing 64 nodelets in the Chick system. We also define and justify relative metrics to compare prototype FPGA-based hardware with established ASIC architectures. The Chick currently supports up to 68x scaling for graph alignment, 80 MTEPS for BFS on balanced graphs, and 50% of measured STREAM bandwidth for SpMV.

Hein, Eric↗
DOE OSTI2023

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application-Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frame-works), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This paper provides an overview of the flow in the context of the generation of accelerators for edge processing to be integrated in transmission electron microscopy (TEM) devices, focusing on use cases from precision material synthesis. We show the tool in action with an example of design space exploration for inference on reconfigurable devices with a conventional deep neural network model (LeNet). Finally, we discuss the research directions and opportunities enabled by SODA in the area of autonomous control for scientific experimental workflows.

Castellana, Vito G.↗
DOE OSTI2025

pnnl/soda-benchmarks

The SODA-Benchmarks repository (currently hosted at: https://gitlab.pnnl.gov/sodalite/soda-benchmarks) provides a comprehensive benchmark suite for evaluating tools within the SODA (Software-Defined Accelerators) toolchain, which focuses on hardware/software co-design and accelerator generation for FPGAs and ASICs

Agostini, Nicolas [Pacific Northwest National Labo↗
DOE OSTI2025

Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0

This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).

Shalf, JohnM. [Lawrence Berkeley National Laborato↗
DOE OSTI2022

Market Research Study: Applications of ASCR HPC Software

The Department of Energy (DOE)’s Advanced Scientific Computing Research (ASCR) program has developed hundreds of software tools for high performance computing (HPC). Although many HPC hardware advances have permeated the market, such as CPUs, GPUs, TPUs and ASICs, the software developed by DOE for different HPC applications has not necessarily been mined. The DOE is interested in making its HPC software portfolio available to the public in order to maximize the value of what has been developed.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Intelligent Proppants for Hydraulic Fracture Diagnostics

This Phase 1 Report details our Phase 1 progress in proving the feasibility of a highly integrated, highly miniaturized sensor ball. The ball contains sensors, analog to digital converters, memory, a clock, and an acoustic communications module all integrated onto a single silicon chip. Phase 2 is to focus on the application specific integrated circuit (ASIC). Phase 1 piecewise proves the feasibility of this innovation by examining a few critical subsystems including the communications module and inertial sensor performance. Acoustic simulations of an acoustically active and traceable proppant are also performed and summarized in this report.

01 COAL, LIGNITE, AND PEAT↗
DOE OSTI2023

A Digital System-On-Chip CO 2 Sensor (Final Report)

The overall goal of the project was to build a low-cost digital CO 2 sensor made of N5’s patented sensing architecture using a digital application specific integrated circuit (ASIC) to reduce the amount of energy usage in residential and commercial buildings. The proposed small form-factor CO 2 monitoring device contains a molecular sieve membrane filter capable of monitoring indoor air quality which indicates the content of CO 2 inside a residential or commercial building.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Scalable Skipper-CCD Analog Readout Electronics (SSCARE) for the Massive Multichannel OSCURA Experiment

We present a multiplexed analog readout electronics system for Skipper-CCDs based on the MIDNA ASIC. It allows for subelectron noise-level operation while maintaining a minimal number of acquisition channels. In addition, it requires low-disk storage and low-bandwidth data transfer with zero added multiplexing time during the simultaneous operation of thousands of channels. We describe the implementation of such a system in a new instrument composed by 16 sensors operated with a two-stage analog multiplexed readout scheme. The instrument is a part of the R&D effort of the OSCURA experiment.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Smart Pixels: towards on-sensor inference of charged particle track parameters and uncertainties

The combinatorics of track seeding has long been a computational bottleneck for triggering and offline computing in High Energy Physics (HEP), and remains so for the HL-LHC. Next-generation pixel sensors will be sufficiently fine-grained to determine angular information of the charged particle passing through from pixel-cluster properties. This detector technology immediately improves the situation for offline tracking, but any major improvements in physics reach are unrealized since they are dominated by lowest-level hardware trigger acceptance. We will demonstrate track angle and hit position prediction, including errors, using a mixture density network within a single layer of silicon as well as the progress towards and status of implementing the neural network in hardware on both FPGAs and ASICs.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗