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At least 289 records · Page 16

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

An Offload NIC for NASA, NLR, and Grid Computing

This work addresses distributed data management and access dynamically configurable high-speed access to data distributed and shared over wide-area high-speed network environments. An offload engine NIC (network interface card) is proposed that scales at nX10-Gbps increments through 100-Gbps full duplex. The Globus de facto standard was used in projects requiring secure, robust, high-speed bulk data transport. Novel extension mechanisms were derived that will combine these technologies for use by GridFTP, bandwidth management resources, and host CPU (central processing unit) acceleration. The result will be wire-rate encrypted Globus grid data transactions through offload for splintering, encryption, and compression. As the need for greater network bandwidth increases, there is an inherent need for faster CPUs. The best way to accelerate CPUs is through a network acceleration engine. Grid computing data transfers for the Globus tool set did not have wire-rate encryption or compression. Existing technology cannot keep pace with the greater bandwidths of backplane and network connections. Present offload engines with ports to Ethernet are 32 to 40 Gbps f-d at best. The best of ultra-high-speed offload engines use expensive ASICs (application specific integrated circuits) or NPUs (network processing units). The present state of the art also includes bonding and the use of multiple NICs that are also in the planning stages for future portability to ASICs and software to accommodate data rates at 100 Gbps. The remaining industry solutions are for carrier-grade equipment manufacturers, with costly line cards having multiples of 10-Gbps ports, or 100-Gbps ports such as CFP modules that interface to costly ASICs and related circuitry. All of the existing solutions vary in configuration based on requirements of the host, motherboard, or carriergrade equipment. The purpose of the innovation is to eliminate data bottlenecks within cluster, grid, and cloud computing systems, and to add several more capabilities while reducing space consumption and cost. Provisions were designed for interoperability with systems used in the NASA HEC (High-End Computing) program. The new acceleration engine consists of state-ofthe- art FPGA (field-programmable gate array) core IP, C, and Verilog code; novel communication protocol; and extensions to the Globus structure. The engine provides the functions of network acceleration, encryption, compression, packet-ordering, and security added to Globus grid or for cloud data transfer. This system is scalable in nX10-Gbps increments through 100-Gbps f-d. It can be interfaced to industry-standard system-side or network-side devices or core IP in increments of 10 GigE, scaling to provide IEEE 40/100 GigE compliance.

Awrach, James↗

The ETROC Project: Precision Timing ASIC Development for LGAD-based CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD silicon devices to be read out by ETROCs for precision timing measurement with down to 30 ps timing resolution. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel cell being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. Approximately 15% of the sensors near the highest eta region will experience hadron fluence above 1e15 neq/cm² towards end of operation of HL-LHC, resulting in small signal amplitude with LGAD gain reduced to around 10. For this reason, the front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile.

97 MATHEMATICS AND COMPUTING↗

X-ray Characterization of a Multichannel Smart-Pixel Array Detector

The Voxtel VX-798 is a prototype X-ray pixel array detector (PAD) featuring a silicon sensor photodiode array of 48 x 48 pixels, each 130 mu m x 130 mu m x 520 mu m thick, coupled to a CMOS readout application specific integrated circuit (ASIC). The first synchrotron X-ray characterization of this detector is presented, and its ability to selectively count individual X-rays within two independent arrival time windows, a programmable energy range, and localized to a single pixel is demonstrated. During our first trial run at Argonne National Laboratory's Advance Photon Source, the detector achieved a 60 ns gating time and 700 eV full width at half-maximum energy resolution in agreement with design parameters. Each pixel of the PAD holds two independent digital counters, and the discriminator for X-ray energy features both an upper and lower threshold to window the energy of interest discarding unwanted background. This smart-pixel technology allows energy and time resolution to be set and optimized in software. It is found that the detector linearity follows an isolated dead-time model, implying that megahertz count rates should be possible in each pixel. Measurement of the line and point spread functions showed negligible spatial blurring. When combined with the timing structure of the synchrotron storage ring, it is demonstrated that the area detector can perform both picosecond time-resolved X-ray diffraction and fluorescence spectroscopy measurements.

CMOS ASIC↗

A linear array of position-sensitive virtual Frisch-grid CdZnTe for low-energy gamma rays

Large-area arrays of position-sensitive virtual Frisch-grid CdZnTe (CZT) detectors with enhanced energy resolution and high efficiency have been proposed for spectroscopy and imaging of gamma-ray sources. We present the design and test results of a linear array of such detectors optimized for use in handheld instruments. There are several application areas for such detectors including uranium enrichment measurements, storage monitoring, dosimetry and other nuclear safeguards related tasks. The array configuration provides a large area with minimum number of readout channels, which potentially allows the developers to avoid using ASIC-based readout electronics by substituting it with hybrid preamplifiers followed by digitizers. The array prototype consists of 6 5 x 7 x 25 mm 3 CZT detectors side-oriented with respect to the source to achieve the maximum area. Each detector is furnished with 5 mm-wide charge-sensing pads placed near the anode. As an option, the pads can be grouped together to reduce the number of readout channels. The same can be done with the cathodes. The pads signals are converted into X–Y coordinates and combined with the cathode signals (for the Z coordinates) to give 3D positional information of each interaction point. This information is used to correct the response non-uniformity caused by material inhomogeneity, which allows the developers to use standard grade (unselected) CZT crystals, while retaining high spectroscopic performance.

3D position-sensitive virtual Frisch-grid detector↗

Multiplicity trigger detector for the S π RIT experiment

A multiplicity trigger detector (MTD) was developed for the SπRIT experiment that aims to probe the high- density symmetry energy via heavy-ion collisions (HICs). The MTD is designed to measure the charged-particle multiplicity in HICs to provide a trigger signal that can be used to select high-multiplicity events induced by central collisions. The MTD consists of two side-walls segmented into 30 plastic scintillation paddles, each equipped with a multi-pixel photon counter. A custom board with EASIROC front-end ASIC is used as readout electronics. A multiplicity logic signal is generated by an on-board FPGA that processes the discriminated signals from EASIROCs. The overall latency of the whole detector system for outputting the trigger is less than 100 ns, including 52 ns of electronics latency for processing the signals. During the measurement of 112 Sn + 124 Sn reactions at an incident energy of 270 MeV/nucleon, the minimum multiplicity threshold of the MTD was set to 4, where the overall trigger efficiency was obtained to be about 39 % for inclusive nuclear reactions. Furthermore, a simulation study with a numerical calculation of HICs found that the central collisions of impact parameters of less than 4 fm can be triggered with a high efficiency of more than 95 % by the experimental trigger condition.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

3x3 array module of 8×8×32 mm 3 position-sensitive virtual frisch-grid CdZnTe detectors for imaging and spectroscopy of cosmic gamma-rays

Here, we evaluated the performance of the 3x3 array of 32-mm long position-sensitive virtual Frisch-grid (VFG) CdZnTe (CZT) detectors read out by the IDEAS GDS-100 data acquisition system. The array is a mechanically solid module designed for integration into a large effective area gamma-ray telescope proposed for imaging and spectroscopy of cosmic gamma-rays. The array employs the bar-shaped 8x8x32 mm 3 CZT crystals which recently became available from Redlen Technologies, Inc. and Kromek-eV Group PLC at affordable costs. The waveform sampling IDE3421 application-specific integrated circuit (ASIC), developed by the University of Michigan and IDEAS for CZT pixel detectors, was adapted to capture the signals from the array's VFG detectors. We showed good spectral performance of the Redlen detectors with an energy resolution of <1% FWHM at 662 keV and slightly poorer performance of the Kromek-eV detectors with a resolution of <2% measured at a reduced temperature of 13 °C. By testing the same detectors as single devices using hybrid charge-sensitive preamplifiers, we demonstrated improved energy resolutions at a normal temperature of ~25°C: <1% and 1.3-1.7%, respectively. However, the Kromek-eV detectors did not perform as well as the Redlen ones. We explained this by the space charge formation (polarization) decreasing the electric field and the electron drift times. The polarization was likely caused by the high injections of holes from the anode contacts. The absence of polarization in Redlen detectors suggested that the quality of the contacts might have played a role in this case.

47 OTHER INSTRUMENTATION↗

Signal formation and sharing in AC-LGADs using the ALTIROC 0 front-end chip

The development of detectors that provide high resolution in four dimensions has attracted wide-spread interest in the scientific community for applications in high-energy physics, nuclear physics, medical imaging, mass spectroscopy as well as quantum information. However, finding a technology capable of fulfilling such aspiration proved to be an arduous task. Among other silicon-based candidates, the Low-Gain Avalanche Diode (LGAD) has already shown excellent timing performances but proved to be unsuitable for fine pixelization. Therefore, the AC-coupled LGAD (AC-LGAD) approach was introduced to provide high resolution in both time and space, making it a promising candidate for future 4D detectors. However, appropriate readout electronics must be developed to match the sensor's fast-time and fine-pitch capabilities. This is currently a major technological challenge. Here, we test AC-LGAD prototypes read out by the fast-time ASIC ALTIROC 0, originally developed for the readout of DC-coupled LGADs for the ATLAS experiment at the High Luminosity-LHC. Signal generated by either betas from a 90 Sr source or a focused infra-red laser were analyzed. This paper details the first successful readout of an AC-LGAD sensor using a readout chip. This result will pave the way for the design and construction of a new generation of AC-LGAD-based 4D detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Design and Performance Testing of a Linear Array of Position-Sensitive Virtual Frisch-Grid CdZnTe Detectors for Uranium Enrichment Measurements

Abstract— Arrays of position-sensitive virtual Frisch-grid CdZnTe (CZT) detectors with enhanced energy resolution have been proposed for spectroscopy and imaging of gamma-ray sources in different applications. The flexibility of the array design, which can employ CZT crystals with thicknesses up to several centimeters in the direction of electron drift, allows for integration into different kinds of field-portable instruments. These can include small hand-held devices, compact gamma cameras and large field-of-view imaging systems. In this work, we present results for a small linear array of such detectors optimized for the low-energy region, 50-400 keV gamma-rays, which is principally intended for incorporation into hand-held instruments. There are many potential application areas for such instruments, including uranium enrichment measurements, storage monitoring, dosimetry and other safeguards-related tasks that can benefit from compactness and isotope-identification capability. The array described here provides a relatively large area with a minimum number of readout channels, which potentially allows the developers to avoid using an ASIC-based electronic readout by substituting it with hybrid preamplifiers followed by digitizers. The array prototype consists of six (5x5.7x25 mm3) CZT detectors positioned in a line facing the source to achieve a maximum exposure area (~10 cm2). Each detector is furnished with 5 mm-wide charge-sensing pads placed near the anode. The pad signals are converted into X-Y coordinates for each interaction event, which are combined with the cathode signals (for determining the Z coordinates) to give 3D positional information for all interaction points. This information is used to correct the response non-uniformity caused by material inhomogeneity, which therefore allows the usage of standard-grade (unselected) CZT crystals, while achieving high-resolution spectroscopic performance for the instrument. In this presentation we describe the design of the array, the results from detailed laboratory tests, and preliminary results from measurements taken during a field test.

36 MATERIALS SCIENCE↗

Design and Performance Testing of a Linear Array of Position-Sensitive Virtual Frisch-Grid CdZnTe Detectors for Uranium Enrichment Measurements

Arrays of position-sensitive virtual Frisch-grid CdZnTe (CZT) detectors with enhanced energy resolution have been proposed for spectroscopy and imaging of gamma-ray sources in different applications. The flexibility of the array design, which can employ CZT crystals with thicknesses up to several centimeters in the direction of electron drift, allows for integration into different kinds of field-portable instruments. These can include small hand-held devices, compact gamma cameras and large field-of-view imaging systems. In this work, we present results for a small linear array of such detectors optimized for the low-energy region, 50-400 keV gamma-rays, which is principally intended for incorporation into hand-held instruments. There are many potential application areas for such instruments, including uranium enrichment measurements, storage monitoring, dosimetry and other safeguards-related tasks that can benefit from compactness and isotope-identification capability. The array described here provides a relatively large area with a minimum number of readout channels, which potentially allows the developers to avoid using an ASIC-based electronic readout by substituting it with hybrid preamplifiers followed by digitizers. The array prototype consists of six (5x5.7x25 mm3) CZT detectors positioned in a line facing the source to achieve a maximum exposure area (~10 cm2). Each detector is furnished with 5 mm-wide charge-sensing pads placed near the anode. The pad signals are converted into X-Y coordinates for each interaction event, which are combined with the cathode signals (for determining the Z coordinates) to give 3D positional information for all interaction points. This information is used to correct the response non-uniformity caused by material inhomogeneity, which therefore allows the usage of standard-grade (unselected) CZT crystals, while achieving high-resolution spectroscopic performance for the instrument. In this presentation we describe the design of the array, the results from detailed laboratory tests, and preliminary results from measurements taken during a field test.

36 MATERIALS SCIENCE↗

Noise Characterization and Filtering in the MicroBooNE Liquid Argon TPC

The low-noise operation of readout electronics in a liquid argon time projection chamber (LArTPC) is critical to properly extract the distribution of ionization charge deposited on the wire planes of the TPC, especially for the induction planes. This paper describes the characteristics and mitigation of the observed noise in the MicroBooNE detector. The MicroBooNE's single-phase LArTPC comprises two induction planes and one collection sense wire plane with a total of 8256 wires. Current induced on each TPC wire is amplified and shaped by custom low-power, low-noise ASICs immersed in the liquid argon. The digitization of the signal waveform occurs outside the cryostat. Using data from the first year of MicroBooNE operations, several excess noise sources in the TPC were identified and mitigated. The residual equivalent noise charge (ENC) after noise filtering varies with wire length and is found to be below 400 electrons for the longest wires (4.7 m). The response is consistent with the cold electronics design expectations and is found to be stable with time and uniform over the functioning channels. This noise level is significantly lower than previous experiments utilizing warm front-end electronics.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Smart Pixel Sensors for the HL-LHC

Large-scale particle physics experiments produce tens of terabytes of data every second. Innovative methods to manage the data rate at the HL-LHC, which expects to operate at 10x the luminosity of what the LHC was initially designed for, are needed. AI-on the chip provides a way to intelligently filter out low momentum clusters in the pixel detector. This will open up an opportunity to use the pixel detector for the first time in the CMS Level-1 trigger, and lead to increased sensitivity to new physics measurements and searches. We have taped out our first chip, which incorporates a $p_T$ filtering algorithm on an ASIC chip. Our initial $p_T$ filtering algorithm considers clusters that are tracked by CMS. We will report on ongoing studies seeking to enhance the performance of our filter by utilizing unsupervised learning on untracked clusters, thus increasing background rejection.

43 PARTICLE ACCELERATORS↗

FPGA Mitigation Strategies for Critical Applications

Technology is changing at a fast pace. Transistor geometries are getting smaller, voltage thresholds are getting lower, design complexity is exponentially increasing, and user options are expanding. Consequently, reliable insertion of error detection and correction (EDAC) circuitry has become relatively challenging. As a response, a variety of mitigation techniques are being evaluated. They range from weak EDAC circuits that save area and power to strong mitigation strategies that are a great expense to systems. This presentation will focus on radiation induced susceptibilities for a variety of FPGA types and ASIC devices. In addition, the user will be provided information on applicable mitigation strategies per device.

Berg, Melanie↗

Flexible High Speed Codec (FHSC)

The ongoing NASA/Harris Flexible High Speed Codec (FHSC) program is described. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K emitter coupled logic (ECL) which can be easily translated to an ECL gate array.

Segallis, G. P.↗

Flexible high speed CODEC (FHSC)

This paper describes the on going NASA/Harris FHSC CODEC program. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K ECL logic which can be easily translated to an ECL gate array.

Segallis, G. P.↗

The STAR Forward Silicon Tracker

The Forward Silicon Tracker (FST) is a pivotal component of the forward upgrade of the Solenoidal Tracker at RHIC (STAR), designed to discern hadron charge signs with a momentum resolution better than 30% for 0.2 < p T < 2GeV/c in the 2.5 < η < 4 pseudorapidity range. Its compact design features three disks along the beam direction, minimized material budget, and scattering effects. The FST uses Hamamatsu’s p-in-n silicon strip sensors with a double metal layer that enables efficient signal routing to the readout electronics, enhancing overall detector performance. The flexible hybrid boards, essential for the readout system, are constructed with Kapton and copper layers to optimize signal handling and power distribution. These boards connect silicon strips to analogue pipeline ASIC APV25-S1 chips, which read up to 128 channels each. A cooling system with nonconducting, volatile NOVEC 7200 coolant at 22.2 °C mitigates ASIC-generated heat. Furthermore, the FST enhances forward tracking performance at STAR as an integral part of the forward upgrade.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC

The MIDNA application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65 nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm${^2}$ area and has an input referred noise of 2.7${\mu\nu}_{rms}$. It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Here, sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2${e^{-}}$ RMS by averaging 1000 samples with MIDNA both at room temperature and at 180 Kelvin.

1/f noise↗

Structure of Nuclei Far From Stability

The work performed under this grant has led to the development of a detection system that will be used to measure reaction rates for proton or neutron capture reactions at stellar energies on radioactive ions far from stability. The reaction rates are needed to better understand the physics of nucleosynthesis in explosive stellar processes such as supernovae and X-ray burst explosions. The radioactive ions will be produced at the Radioactive Ion Beam Facility (RIBF) at RIKEN near Tokyo, Japan. During the course of this work, the group involved in this project has expanded by several institutions in Europe and Japan and now involves collaborators from the U.S., Japan, Hungary, Romania, Germany, Spain, Italy, China, and South Korea. As part of the project, a novel design based on large-area silicon detectors has been built and tested and the performance characterized in a series of tests using particle beams with a variety of atomic numbers at the Cyclotron Institute of Texas A&M University and the Heavy Ion Medical Accelerator in Chiba facility (HIMAC) in Chiba, Japan. The work has involved mechanical construction of a special purpose vacuum chamber, with a precision mounting system for the silicon detectors, development of a new ASICs readout system that has applications with a wide variety of silicon detector systems, and the development of a data acquisition system that is integrated into the computer system being used at RIBF. The parts noted above that are needed to carry out the research program are completed and ready for installation. Several approved experiments that will use this system will be carried out in the near future. The experimental work has been delayed due to a large increase in the cost and availability of electrical power for RIBF that occurred following the massive earthquake and tsunami that hit Japan in the spring of 2011. Another component of the research carried out with this grant involved developing the theoretical tools that are required to extract the information from the experiments that is needed to determine the stellar reaction rates. The tools developed through this part of the work will be made freely available for general use.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗