Search NASA⌕ Search

SEARCH · Search NASA

Results for “FPGA”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 289 records · Page 16

Low duty cycle pulsed UV technique for spectroscopy of aluminum monochloride

We present what we believe to be a novel technique to minimize UV-induced damage in experiments that employ second-harmonic generation cavities. The principle of our approach is to reduce the duty cycle of the UV light as much as possible to prolong the lifetime of the used optics. The low duty cycle is achieved by ramping the cavity into resonance for a short time during the experimental cycle when the light is used and tuning it to an off-resonant state otherwise. The necessary fast ramp and length-stabilization control of the cavity is implemented with the FPGA-based STEMlab platform. We demonstrate the utility of this method by measuring the isotope shift of the electronic transition (X 1 Σ ← A 1 Π) in AlCl at 261.5 nm in a pulsed molecular beam experiment.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗

Disentangling Beam Losses in The Fermilab Main Injector Enclosure Using Real-Time Edge AI

The Fermilab Main Injector enclosure houses two accelerators, the Main Injector and Recycler Ring. During normal operation, high intensity proton beams exist simultaneously in both. The two accelerators share the same beam loss monitors (BLM) and monitoring system. Deciphering the origin of any of the 260 BLM readings is often difficult. The (Accelerator) Real-time Edge AI for Distributed Systems project, or READS, has developed an AI/ML model, and implemented it on fast FPGA hardware, that disentangles mixed beam losses and attributes probabilities to each BLM as to which machine(s) the loss originated from in real-time. The model inferences are then streamed to the Fermilab accelerator controls network (ACNET) where they are available for operators and experts alike to aid in tuning the machines.

43 PARTICLE ACCELERATORS↗

Redesign of the Timeline Generator at Fermilab using a web-based Flutter application, GraphQL API and an IOC

The control system at Fermilab is undergoing an evolution with a shift towards web-based applications with connections to the EPICS infrastructure. The Timeline Generator (TLG) is an application that serves to coordinate events across the lab using different timing links. These links include the Tevatron clock (TCLK), a 10 MHz serial link with events encoded at 20Hz and Machine Data (MDAT), a communication link with states encoded at 720Hz. This paper covers the redesign of the major components of the TLG. This includes a web-based Flutter application for building timelines. A placement service is in use that has a GraphQL interface and uses a timeline input to compute a schedule of events and states. The Flutter application sends this computed schedule to the TLG IOC via a GraphQL interface to the Data Pool Manager (DPM). The TLG IOC runs on an Arria FPGA, the Accelerator Clock Generator (ACLK-GEN), which is responsible for writing the events and states on to the different timing links.

Carmichael, Linden [Fermilab]↗

Proton pulse charge calculation algorithm in Beam Power Limiting System at Spallation Neutron Source

A proton pulse charge calculation algorithm in the Beam Power Limiting System (BPLS) at the Spallation Neutron Source (SNS) was developed and implemented in an FPGA. The algorithm calculates one-minute running average of the pulse charges and issues a fault to the Personal Protection System (PPS) and the Machine Protection System (MPS) when a limit is reached. A bit-accurate model of the algorithm was first developed and tested in Matlab® and then implemented and simulated in VHDL using Vivado® design environment. Finally, the algorithm was verified on a µTCA-based hardware platform.

Bobrek, Miljko [ORNL] (ORCID:0000000332763451)↗

Optimizing Mu2e Spill Regulation System Algorithms

A slow extraction system is being developed for the Fermilab’s Delivery Ring to deliver protons to the Mu2e experiment. During the extraction, the beam on target experiences small intensity variations owing to many factors. Various adaptive learning algorithms will be employed for beam regulation to achieve the required spill quality. We discuss here preliminary results of the slow and fast regulation algorithms validation through the computer simulations before their implementation in the FPGA. Particle tracking with sextupole resonance was used to determine the fine shape of the spill profile. Fast semi-analytical simulation schemes and Machine Learning models were used to optimize the fast regulation loop.

43 PARTICLE ACCELERATORS↗

JLAB LLRF 3.0 Development and Tests

The Jefferson Lab LLRF 3.0 system is being developed to replace legacy LLRF systems in the CEBAF accelerator. The new design builds upon 25 years of design and operational RF control experience, and our recent collaboration in the design of the LCLSII LLRF system. The new cavity control algorithm is a fully functional phase and amplitude locked Self Exciting Loop (SEL). This paper discusses the progress of the LLRF 3.0 hardware design, FPGA firmware development, User Datagram Protocol (UDP) operation, and recent LLRF 3.0 system tests on the CEBAF Booster cryomodule in the Upgrade Injector Test Facility (UITF).

Plawski, T. E.↗

Performance of the LLRF System for the Fermilab PIP-II Injector Test

PIP-II IT is a test facility for the PIP-II project where the injector, warm front-end, and the first two superconducting cryomodules are being tested. The 8-cavity half-wave-resonator (HWR) cryomodule operating at 162.5 MHz is followed by the 8-cavity single-spoke resonator(SSR1) cryomodule operating at 325 MHz. The LLRF systems for both cryomodules are based on a common SOC FPGA-based hardware platform. The resonance control systems for the two cryomodules are quite different, the first being a pneumatic system based on helium pressure and the latter a piezo/stepper motor type control. The data acquisition and control system can support both CW and Pulsed mode operations. Beam loading compensation is available which can be used for both manual/automatic control in the LLRF system. The user interfaces include EPICS, Labview, and ACNET. Testing of the RF system has progressed to the point of being ready for a 2 mA beam to be accelerated to 25 MeV. The design and performance of the field control and resonance control system operation with beam are presented in this paper.

43 PARTICLE ACCELERATORS↗

Synchronization and phase locking of resonant magnet power supplies for Mu2e experiment at Fermilab

The Mu2e Experiment has stringent beam structure requirements; namely, it requires short (~200 ns) proton bunches separated by 1.5-2.0 $\mu$s. This beam structure will be produced using the Fermilab 8 GeV Booster, the 8 GeV Recycler Ring, and the Delivery Ring, which was formerly part of the antiproton accumulator system. Out of time beam is limited to a fraction of level of no more than $1\times 10^{-10}$, a requirement known as "extinction". Achieving this level of extinction requires a system of resonant magnets and collimators, phased such that only in time particles will pass through. The Mu2e magnet system involves two components: a 300 kHz component, timed such that the 600 kHz beam will pass through the collimators at the nodes, and a 4.5 MHz system to reduce the slewing of the in-time beam. These two systems must be precisely phase locked to the bunch rate coming from the Delivery Ring, which itself must be phased to match beam transfers coming from the Recycler. This poster describes the control system for the magnets, which is based on an Intel Arria FPGA, which handles phase locking of the magnets to the Delivery Ring, including the phase jumps required to match transfers from the Recycler.

43 PARTICLE ACCELERATORS↗

Evaluation of the first version of the new RFPI system dedicated to PIP-II project accelerator

The Low-Level Radio Frequency (LLRF) control system is one of the most critical superconducting linac infrastructures responsible for the parameters of the beam acceleration. The LLRF system mainly focuses on the electromagnetic field parameters inside the cavity. While it incorporates fast feedback algorithms to optimize energy transfer to the passing particle beam it does not follow other cryomodule or cavity parameter changes. The Radio Frequency Protection Interlock (RFPI) system closely monitors various factors (like cryomodule vacuum, beamline vacuum, field emission probe current level, temperature, RF signal leakage, etc). Its simple but reliable logic has to provide an instant decision about the LLRF system or high-power amplifier output signal blocking in case of safety region excitation. This contribution presents a new version of the RFPI system which logic is implemented in the FPGA chip. The initial work on the prototype of the new system design resulted in the PoC (Proof of Concept) device. The PoC offers the possibility of various protection logic configurations, input signals parameters evaluation, and modularity aspects verification. The structure and test results from the device evaluation are summarized and discussed in this contribution.

43 PARTICLE ACCELERATORS↗

DIRECT RF SAMPLING BASED LLRF CONTROL SYSTEM FOR C-BAND LINEAR ACCELERATOR

Low Level RF (LLRF) control systems of linear accel- erators (LINACs) are typically implemented with hetero- dyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Fre- quency System-on-Chip (RFSoC) device from AMD Xilinx integrates data converters with maximum RF frequency of 6 GHz. This enables direct RF sampling of C-band LLRF signal typically operated at 5.712 GHz without any analogue mixers, which can significantly simplify the system architec- ture. The data converters sample RF signals in higher order Nyquist zones and then up or down convert digitally by the integrated data path in RFSoC. The closed-loop feedback control firmware implemented in FPGA integrated in RF- SoC can process the base-band signal from the ADC data path and calculate the updated phase and amplitude to be up- mixed by the DAC data path. We have developed a C-band LLRF control RFSoC platform with direct RF sampling, which targets Cool Copper Collider (𝐶3) and other C or S band LINAC research and development projects. In this paper, the architecture of the platform will be described. We have optimized the configuration of the data converter and characterized performance of them with RF pulses. The test results for some of the key performance parameters for the LLRF platform with our custom solid-state amplifier, such as phase and amplitude stability, will be discussed in this paper.

Liu, C↗

Flattening the field during injection in the Fermilab booster using dipole corrector magnets

The FNAL Booster is a fast cycling 15 Hz resonant circuit synchrotron accelerating proton beam from 400 MeV to 8 GeV. The linac pulse injected into the Booster is ~32 μsec long and fills the ring by multi-turn charge-exchange injection. As part of the PIP-II project, the Booster injection energy and repetition rate will be increased to 800 MeV and 20 Hz respectively. Due to much reduced average current in the new superconducting PIP-II linac, the injection time will increase to 550 μs. A shorter machine cycle coupled to a longer injection time make flattening the injection porch B-field during injection important requirement for successful PIP-II operation. We aim to achieve: (1) flattening of the net bending during injection using dipole correctors, and (2) using a new system based on an Altera FPGA board, reduction of the cycle-to-cycle bending field variation caused by current jitter in the Gradient Magnet Power Supply (GMPS). While the flat injection scheme is essential to future PIP-II operations, it should also noticeably improve efficiency for present HEP operations.

43 PARTICLE ACCELERATORS↗

Annual LDRD Report (FY2019)

The performance of Nuclear Deterrence (ND) systems could be improved by adopting advanced commercial CMOS technologies. However, the radiation hardness of these ND systems must be assured. This project quantified dose rate upset thresholds, allowing us to evaluate whether advanced commercial technologies can be used in rad hard applications. This project also evaluated the susceptibility of advanced commercial technologies to neutron displacement damage and single event effects, and developed hardness assurance methods. As a result of this work, Sandia is now collaborating more closely with DoD agencies and their contractors to understand and improve the radiation hardness of advanced commercial technologies. Sandia Capabilities (SPHINX, lon Beam Lab, FPGA test capabilities) were developed and are being utilized by other programs. Staff were trained to do radiation survivability testing and developed proposals that were funded. Internal and external collaborations and partnerships were developed, including with Georgia Tech. This project received the Best Paper award at the 2019 Hardened Electronics And Radiation Technology (HEART) Conference.

36 MATERIALS SCIENCE↗

Hardware Evaluation Analytical Modeling and Node Simulation: Benefits of Tighter GPU Integration

In this report, we examine several emerging technologies of interest to the Department of Energy and its computational centers. These include: 1) quantifying the benefit of tighter CPU-GPU integration, 2) quantifying the appropriate CPU core:GPU ratio, 3) quantifying the penalty for CPU-GPU disaggregation, 4) quantifying the benefits of tighter GPU-GPU integration, 5) quantifying the benefits of unified memory, and 6) quantifying the benefits of tighter FPGA-GPU integration.

97 MATHEMATICS AND COMPUTING↗

Autonomous System Subversion Tactics: Prototypes and Recommended Countermeasures

One of the fielding requirements for Advanced and Small Modular Reactors (AR/SMR) is the ability to support remote and autonomous operations. Autonomous Control Systems (ACS) are found on platforms such as Autonomous Space Vehicles, Cruise Missiles, and advanced driver-assistance systems. Each of these ACS implementations depends upon a set of decision support subsystems responsible for supporting Autonomous Mission Managers (names vary based upon field and author preferences). These Autonomous Mission Managers receive inputs from system sensors (e.g., LIDAR collection from an automobile travelling down a street; transients from a nuclear reactor), and perform a set of classifications (e.g., Red Traffic Light; Small Pedestrian at 10m; Load Rejection; Single Coolant Pump Trip), and then use these classifications in combination with recommendation algorithms to achieve platform goals (e.g., Stop the Vehicle at the Traffic Light, Avoid the Small Pedestrian; Trip the Reactor to prevent a Safety Event). The design, implementation, and fielding of an ACS capability will alter the cyber-attack surface such that existing risk management plans will need to be updated to include how to protect and defend against data-science and decision-support-system attack classes. These attack classes would include protection of the design and training environments where algorithm selection and testing and training data would be obvious attack vectors. These attack classes would also require an informed set of detection and response procedures to identify anomalous behaviors and document best practices for anomaly assessment and vulnerability mitigation and remediation. Last year we published a Cyber Threat Assessment Methodology for Autonomous and Remote Operations for AR/SMRs along with a companion publication on Cyber Attack and Defense Use Cases. The focus of the methodology was on describing and enumerating ACS processes, components, and functions such that security engineers could: evaluate subversion options against the target; identify threat actor attributes and capabilities derived from each subversion option; and identify security controls and response countermeasures. The Use Cases document offered detailed methodology examples including an assessment of a Military Base SMR, an Autonomous System Decision Loop, and implementation of AR/SMR Machine Learning algorithms. Our proposal at the end of last year was to focus on implementation of subversion prototypes related to the last Use Case area: AR/SMR Machine Learning (ML) Algorithms. We included six attack scenarios in our Use Cases paper: a Poisoning Attack against ML functions implemented using an FPGA; a Trojaning Attack against ML classifiers exploiting the excitability of Nuclear Engineers; a Backdooring Attack against ML Training environments to ensure persistence of an attack vector; a False Positive Evasion Attack against multi-factor Access Control Systems using clever inputs; an Inference Attack against ML models by an Insider with access to the Operational environment; and an Adversarial Reprogramming Attack against a Material Access Control Video Surveillance System. At the beginning of this year these six attack scenarios were provided to our research teams at Georgia Tech and Idaho State University and each team successfully implemented a subversion attack against a ML implementation to include transient misclassifications. While this is a notable outcome from this type of research, this paper offers the reader insight into not only how to structure and execute these types of attacks, but into the thought process behind how the researcher investigated the problem space, performed initial algorithm implementation, and the trial-and-error behind arriving at the successful subversion prototypes. We include in this paper a set of associated Scenarios on how these subversion prototypes could be implemented and an initial set of guidance for AR/SMR architects, Nuclear Regulators, and Cyber Defenders to implement awareness and defense capabilities into their current operational portfolios.

42 ENGINEERING↗

SAMPA Based Streaming Readout Data Acquisition Prototype

We have assembled a small-scale streaming data acquisition system based on the SAMPA front-end ASIC. The 32-channel SAMPA chip was designed for the high-luminosity upgrade of the ALICE Time Projection Chamber (TPC) detector at the CERN Large Hadron Collider. The goals of the prototype system are to determine if the SAMPA chip is appropriate for use in detector systems at Jefferson Lab, and to gain experience with the hardware and software required to deploy streaming data acquisition systems in nuclear physics experiments. The 800 channel system is composed of components used in the ALICE TPC data acquisition upgrade. Five front-end cards (FEC) support five SAMPA chips each. SAMPA data streams on an FEC are concentrated into two high-speed (4.48 Gb/s) serial data streams by a pair Gigabit Transceiver ASICs (GBTx). These ten streams (44.8 Gb/s) are transmitted from the FECs over fibers to a PCIe based readout unit. The FPGA engine on the readout unit compresses data for transmission to a server via 100 Gb ethernet. Components on the FECs are radiation tolerant. High data rates can be handled. The system is by design scalable and thus provides a functional prototype for high-rate streaming readout at Jefferson Lab and the future Electron Ion Collider. We have made fundamental measurements (noise, linearity, time resolution) on the SAMPA ASIC. We have also coupled the readout system to a small Gas Electron Multiplier (GEM) detector and have studied its response to cosmic rays. A beam test of the system is planned.

ABBOTT, David↗

Evaluation of a streaming readout solution for Jefferson Lab experiments

Jefferson Lab (JLab) operates the CEBAF accelerator that provides a high energy (up to 12 GeV) and high current (up to 150 µA) polarized electron beam for fixed target experiments. JLab's mission is to provide substantial progress in understanding the Quantum Chromo Dynamics (QCD), the current theory of the spectrum and the dynamics of hadronic matter. Given the broad scientific program a general-purpose detector, CLAS12, has been designed and constructed. Such a detector requires a sophisticated trigger and current experiments use an on-line FPGA-based system that relies upon custom firmware and electronics both of which are difficult reconfigure from one experiment to the next. To overcome these challenges transitioning to a streaming readout has been proposed since it would allow a more flexible, easier to debug, software trigger to be developed. To facilitate this JLab is gaining experience with streaming readout systems and is actively working to design and test a streaming data acquisition architecture. Significant work has already been done to make existing front-end electronics compatible with operation in streaming mode. Software-wise, much work remains to be done but an existing framework, TriDAS, which was developed for underwater neutrino telescopes can, in principle, be used with the existing JLab hardware. A test stand is already in place in the INDRA DAQ development lab at JLab. This paper will present the development of this TriDAS based test system and it?s operation in-beam using parts of the CLAS12 detector to evaluate streaming readout for a large general purpose detector.

Battaglieri, Marco↗

CHG0 to HERO An Update to the Fermilab Booster DCCT

The Booster complex at Fermi National Accelerator Laboratory uses a DC Current Transformer (DCCT) in conjunction with analog circuitry to measure intensity of the circulating beam during the acceleration cycle. This measurement is affectionately known as Charge Zero (CHG0). This platform has been updated to a Bergoz New Parametric Current Transformer (NPCT) and FPGA Data Acquisition System that digitally normalizes beam current to provide a High-quality E12 Read Out (HERO) for the PIP-II era.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗