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At least 289 records · Page 16

High-speed tunable generation of random number distributions using actuated perpendicular magnetic tunnel junctions

Perpendicular magnetic tunnel junctions (pMTJs) actuated by nanosecond pulses are emerging as promising devices for true random number generation (TRNG) due to their intrinsic stochastic behavior and high throughput. In this work, we demonstrate the tunability and quality of random number distributions generated by pMTJs operating at a frequency of 104 MHz. First, changing the pulse amplitude is used to systematically vary the probability bias. The variance of the resulting bitstreams closely matches the expected binomial distribution, demonstrating consistency with an underlying sequence of Bernoulli trials. Second, the quality of uniform distributions of 8-bit random numbers generated with a probability bias of 0.5 is considered. A reduced chi-square analysis of these data shows that only two XOR operations are sufficient to achieve this distribution with p-values greater than 0.05. Finally, we show that there is a correlation between long-term probability bias variations and pMTJ resistance. These findings suggest that variations in the characteristics of the pMTJ underlie the observed variation of probability bias. In conclusion, our results highlight the potential of stochastically actuated pMTJs for high-speed, tunable TRNG applications, showing the importance of the stability of pMTJ device characteristics in achieving reliable, long-term performance.

Magnetic tunnel junctions↗

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗

Influence of birefringent fibre joints on the visibility drift in a Mach – Zehnder interferometer

It is shown that imperfect joints of linear birefringent fibres in a fibre interferometer may result in an uncontrolled visibility drift under varying environmental conditions even with a standard phase matching device. As an example, a double Mach – Zehnder interferometer is considered, which is employed in schemes of quantum key distribution. Results of numerical simulation demonstrate the standard deviation of the quantum bit error rate (QBER), which is comparable to an average QBER value. (paper)

36 MATERIALS SCIENCE↗

Generalized scaling of spin qubit coherence in over 12,000 host materials

Significance Atomic defects in solid-state materials are promising candidates as quantum bits, or qubits. New materials are actively being investigated as hosts for new defect qubits; however, there are no unifying guidelines that can quantitatively predict qubit performance in a new material. One of the most critical property of qubits is their quantum coherence. While cluster correlation expansion (CCE) techniques are useful to simulate the coherence of electron spins in defects, they are computationally expensive to investigate broad classes of stable materials. Using CCE simulations, we reveal a general scaling relation between the electron spin coherence time and the properties of qubit host materials that enables rapid and quantitative exploration of new materials hosting spin defects.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Bistable random momentum transfer in a linear on-chip resonator

Optical switches and bifurcation rely on the nonlinear response of materials. Here, we demonstrate linear temporal bifurcation responses in a passive multimode microresonator, with strongly coupled chaotic and whispering gallery modes (WGMs). In microdisks, the chaotic modes exhibit broadband transfer within the deformed cavities, but their transient response is less explored and yields a random output of the analog signal distributed uniformly from “0” to “1.” Here, we build chaotic states by perturbing the multimode microring resonators with densely packed silicon nanocrystals on the waveguide surface. In vivo measurements reveal random and “digitized” output that ONLY populates around 0 and 1 intensity levels. The bus waveguide mode couples first to chaotic modes, then either dissipates or tunnels into stable WGMs. This binary pathway generates high-contrast, digitized outputs. In conclusion, the fully passive device enables real-time conversion of periodic clock signals into binary outputs with contrasts exceeding 12.3 dB, data rates of up to 10 7 · bits per second, and 20 dB dynamic range.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Jacobian sparsity detection using Bloom filters

Determining Jacobian sparsity structure is an important step in the efficient computation of sparse Jacobians. We introduce a new method for determining Jacobian sparsity patterns by combining bit vector probing with Bloom filters. In conclusion, we further refine Bloom filter probing by combining it with hierarchical probing to yield a highly effective strategy for Jacobian sparsity pattern determination.

Bloom filter↗

Hyperfine and quadrupole interactions for Dy isotopes in DyPc 2 molecules

Nuclear spin levels play a vital role in understanding magnetization dynamics and implementation and control of quantum bits in lanthanide-based single-molecule magnets. We investigate the hyperfine and nuclear quadrupole interactions for 161 Dy and 163 Dy nuclei in anionic DyPc 2 (Pc=phthalocyanine) single-molecule magnets, using multiconfigurational ab initio methods (beyond density-functional theory) including spin–orbit interaction. The two isotopes of Dy are chosen because the others have zero nuclear spin. Both isotopes have the nuclear spin I =5/2, although the magnitude and sign of the nuclear magnetic moment differ from each other. The large energy gap between the electronic ground and first-excited Kramers doublets, allows us to map the microscopic hyperfine and quadrupole interaction Hamiltonian onto an effective Hamiltonian with an electronic pseudo-spin that corresponds to the ground Kramers doublet. Our ab initio calculations illustrate that the coupling between the nuclear spin and electronic orbital angular momentum contributes the most to the hyperfine interaction and that both the hyperfine and nuclear quadrupole interactions for 161 Dy and 163 Dy nuclei are much smaller than those for the 159 Tb nucleus in TbPc 2 single-molecule magnets. The calculated separations of the electronic-nuclear levels are comparable to experimental data reported for 163 DyPc 2 . We demonstrate that hyperfine interaction for the Dy Kramers ion leads to tunnel splitting (or quantum tunneling of magnetization) at zero field. This effect does not occur for TbPc 2 single-molecule magnets. The magnetic field values of the avoided level crossings for 161 DyPc 2 and 163 DyPc 2 are found to be noticeably different, which can be observed from the experiment.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

A Josephson junction with h -BN tunnel barrier: observation of low critical current noise

Decoherence in quantum bits (qubits) is a major challenge for realizing scalable quantum computing. One of the primary causes of decoherence in qubits and quantum circuits based on superconducting Josephson junctions is the critical current fluctuation. Many efforts have been devoted to suppressing the critical current fluctuation in Josephson junctions. Nonetheless, the efforts have been hindered by the defect-induced trapping states in oxide-based tunnel barriers and the interfaces with superconductors in the traditional Josephson junctions. Motivated by this, along with the recent demonstration of 2D insulator h-BN with exceptional crystallinity and low defect density, we fabricated a vertical NbSe 2 /h-BN/Nb Josephson junction consisting of a bottom NbSe 2 superconductor thin layer and a top Nb superconductor spaced by an atomically thin h-BN layer. Furthermore, we characterized the superconducting current and voltage (I–V) relationships and Fraunhofer pattern of the NbSe 2 /h-BN/Nb junction. Notably, we demonstrated the critical current noise (1/f noise power) in the h-BN-based Josephson device is at least a factor of four lower than that of the previously studied aluminum oxide-based Josephson junctions. Our work offers a strong promise of h-BN as a novel tunnel barrier for high-quality Josephson junctions and qubit applications.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Improving wafer-scale Josephson junction resistance variation in superconducting quantum coherent circuits

Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O (100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm 2 . Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having < 1.0% (equivalent to < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Design and performance of an in-vacuum, magnetic field mapping system for the Muon g-2 experiment

The Muon g - 2 experiment at Fermilab (E989) aims to measure the anomalous magnetic moment, a μ , of the muon with a precision of 140 parts-per-billion. This requires a precise measurement of both the anomalous spin precession frequency, ω α , of muons stored in a magnetic field of 1.45 T, and a precise measurement of that magnetic field in terms of the shielded proton Larmor frequency, ω' ρ . The measurement of ω' ρ with a total systematic uncertainty of 70 parts-perbillion involves a combination of various nuclear magnetic resonance (NMR) probes. There are 378 probes mounted in fixed locations that constantly monitor field drifts. A water-based, cylindrical calibration probe provides the calibration in terms of the shielded proton Larmor frequency. A crucial element for the multi-step measurement of ω' ρ is the regular mapping of the magnetic field over the muon storage region. The former experiment at Brookhaven National Laboratory (BNL) employed an in-vacuum field mapping system equipped with 17 NMR probes, which was developed by the University of Heidelberg. We have refurbished and upgraded this system with new probes and electronics. The upgrades include the addition of 16-bit, 1 MSPS digitization of the NMR signals, which replaced the hardware-implemented zero-crossing counting of the system at Brookhaven. The digitized signals offer new capabilities in the NMR frequency analysis and its related systematic uncertainties. To sustain the higher data rates, a new communication scheme with time-division multiplexing was implemented to separate the important NMR reference clock from the data communication in order to reach the specifications for the accuracy and stability of the reference clock. A new barcode reader provides more precise azimuthal position determination during the measurement and calibration. While the mechanical systems that move the field mapper inside the storage ring have been mostly refurbished from BNL, the motion control system was completely replaced with a custom-built electronics centered around a commercial Galil motion controller. Both the field mapping NMR system and its motion control were successfully commissioned at Fermilab and have been in reliable operation during the first three data taking periods of the experiment at Fermilab. Finally, this article will provide the details of the upgrades of the field mapper and its performance.

47 OTHER INSTRUMENTATION↗

Characterization and QC practice of 16-channel ADC ASIC at cryogenic temperature for Liquid Argon TPC front-end readout electronics system in DUNE experiment

ColdADC is a low-noise 16-channel analog-to-digital converter ASIC designed for cold readout electronics of Liquid Argon Time Projection Chambers (LArTPCs) in the Deep Underground Neutrino Experiment (DUNE). ColdADC was specifically designed for operation at cryogenic temperatures (77 K–89 K). Cold electronics is considered to be an enabling technology for liquid argon detectors in neutrino experiments. The main function of the chip is to digitize signals from the 16-channel charge-sensitive amplifier designed at BNL (LArASIC) and send digitized signals to the data aggregator and serializer chip (COLDATA). ColdADC operates with a resolution of 12 bits and a sampling rate of 2 MS/s per channel. A complete characterization of prototype chips was conducted at cryogenic temperature, involving power consumption, noise and linearity performance. In the first DUNE Far-Detector module, 384000 data channels will be read out, corresponding to 24000 ColdADC chips. Therefore, systematic testing of ColdADC chips at cryogenic temperature is vital for the quality and reliability of DUNE Single-Phase modules. We have developed a Quality Control (QC) test stand that includes ColdADC evaluation and characterization at cryogenic temperature. The QC procedure was applied to a first batch of 33 chips, corresponding to 528 data channels. The obtained results meet all the required DUNE specifications for ColdADC. Moreover, the testing outcome allowed us to identify possibilities of performance optimization that are currently being addressed in the design of the next version of the chip. The Quality Control procedure is proved to be successful and will be a reference design for future large-batch production testing of final ColdADC ASICs.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Waveform processing using neural network algorithms on the front-end electronics

In a multi-channel radiation detector readout system, waveform sampling, digitization, and raw data transmission to the data acquisition system constitute a conventional processing chain. The deposited energy on the sensor is estimated by extracting peak amplitudes, area under pulse envelopes from the raw data, and starting times of signals or time of arrivals. However, such quantities can be estimated using machine learning algorithms on the front-end Application-Specific Integrated Circuits (ASICs), often termed as “edge computing”. Edge computation offers enormous benefits, especially when the analytical forms are not fully known or the registered waveform suffers from noise and imperfections of practical implementations. In this work, we aim to predict peak amplitude from a single waveform snippet whose rising and falling edges containing only 3 to 4 samples. We thoroughly studied two well-accepted neural network algorithms, Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) by varying their model sizes. Further, to better fit front-end electronics, neural network model reduction techniques, such as network pruning methods and variable-bit quantization approaches, were also studied. By combining pruning and quantization, our best performing model has the size of 1.5 KB, reduced from 16.6 KB of its full model counterpart. It can reach mean absolute error of 0.034 comparing to that of a naive baseline of 0.135. Such parameter-efficient and predictive neural network models established feasibility and practicality of their deployment on front-end ASICs.

47 OTHER INSTRUMENTATION↗

Multi-channel front-end ASIC for a 3D position-sensitive detector

Arrays of 3D position-sensitive detectors (3DPSD), operating at room temperature and using cadmium zinc telluride (CZT) and thallium bromide (TIBr) sensors, are suitable for gamma-ray spectrometry in many applications. One detector configuration, the 3D position-sensitive Virtual Frisch-Grid detector (VFG), is particularly advantageous for integrating into large area arrays. The signals generated inside each detector of the array are captured with the anode, cathode and four pads that enable the reconstruction of the position and energy of the ionizing interaction by measurements of amplitude and timing of the signals. For these applications, a low-noise front-end ASIC has been developed, capable of processing bipolar signals (needed because of AC-coupling of certain electrodes). The ASIC can be coupled to an ADC in order to form a compound “waveform digitizer” capable of post-processing the analog signals and determining amplitude and timing information. This paper describes a 32-channel front-end ASIC that is suitable for reading out a 3 × 3 or 4 × 4 element matrix in the VFG configuration. Each channel is composed of a low-noise charge amplifier with an adaptive continuous reset feedback circuit suitable for both positive and negative charge, a first order shaper and a single-to-differential converter output stage. Voltage and current references are all internally generated by 10-bit DACs and the chip is fully controllable with the I 2 C communication protocol. The readout channel response has been verified using the implemented injection circuit. Linear behavior up to ~75 ke ± with the gain of ~80 mV/fC, and up to ~200 ke ± with the gain of ~30 mV/fC was demonstrated. In conclusion, the first test result waveforms using a 137 Cs radioactive source on a 5 × 5 × 12 mm 3 TIBr crystal are reported.

47 OTHER INSTRUMENTATION↗

The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC

The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10 –15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

Instruments & Instrumentation↗

QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology

Here, the Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

D-Egg: a dual PMT optical module for IceCube

The D-Egg, an acronym for "Dual optical sensors in an Ellipsoid Glass for Gen2," is one of the optical modules designed for future extensions of the IceCube experiment at the South Pole. The D-Egg has an elongated-sphere shape to maximize the photon-sensitive effective area while maintaining a narrow diameter to reduce the cost and the time needed for drilling of the deployment holes in the glacial ice for the optical modules at depths up to 2700 m. The D-Egg design is utilized for the IceCube Upgrade, the next stage of the IceCube project also known as IceCube-Gen2 Phase 1, where nearly half of the optical sensors to be deployed are D-Eggs. With two 8-inch high-quantum efficiency photomultiplier tubes (PMTs) per module, D-Eggs offer an increased effective area while retaining the successful design of the IceCube digital optical module (DOM). The convolution of the wavelength-dependent effective area and the Cherenkov emission spectrum provides an effective photodetection sensitivity that is 2.8 times larger than that of IceCube DOMs. The signal of each of the two PMTs is digitized using ultra-low-power 14-bit analog-to-digital converters with a sampling frequency of 240 MSPS, enabling a flexible event triggering, as well as seamless and lossless event recording of single-photon signals to multi-photons exceeding 200 photoelectrons within 10 ns. Mass production of D-Eggs has been completed, with 277 out of the 310 D-Eggs produced to be used in the IceCube Upgrade. In this paper, we report the design of the D-Eggs, as well as the sensitivity and the single to multi-photon detection performance of mass-produced D-Eggs measured in a laboratory using the built-in data acquisition system in each D-Egg optical sensor module.

47 OTHER INSTRUMENTATION↗

Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAs

There has been considerable interest and resulting progress in implementing machine learning (ML) models in hardware over the last several years from the particle and nuclear physics communities. A big driver has been the release of the Python package, hls4ml, which has enabled porting models specified and trained using Python ML libraries to register transfer level (RTL) code. So far, the primary end targets have been commercial field-programmable gate arrays (FPGAs) or synthesized custom blocks on application specific integrated circuits (ASICs). However, recent developments in open-source embedded FPGA (eFPGA) frameworks now provide an alternate, more flexible pathway for implementing ML models in hardware. These customized eFPGA fabrics can be integrated as part of an overall chip design. In general, the decision between a fully custom, eFPGA, or commercial FPGA ML implementation will depend on the details of the end-use application. In this work, we explored the parameter space for eFPGA implementations of fully-connected neural network (fcNN) and boosted decision tree (BDT) models using the task of neutron/gamma classification with a specific focus on resource efficiency. We used data collected using an AmBe sealed source incident on Stilbene, which was optically coupled to an OnSemi J-series silicon photomultiplier (SiPM) to generate training and test data for this study. We investigated relevant input features and the effects of bit-resolution and sampling rate as well as trade-offs in hyperparameters for both ML architectures while tracking total resource usage. The performance metric used to track model performance was the calculated neutron efficiency at a gamma leakage of 10 -3 . The results of the study will be used to aid the specification of an eFPGA fabric, which will be integrated as part of a test chip.

47 OTHER INSTRUMENTATION↗

GRAPH — an readout ASIC for large MCP based detectors

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.

47 OTHER INSTRUMENTATION↗