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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

The Galileo Orbiter - Command and telemetry subsystems on their way to Jupiter

An overview is given of the Galileo command and telemetry subsystems, which exemplify the rigid time-synchronized systems required by TDM (time division multiplexing). The spacecraft clock is examined, along with some of the rationale for the development of the clock structure and timing to give a sense of the design imperatives for rigidly synchronized systems. Additional subjects include the structure of the science and engineering frames, emphasizing the subcommutated structure of the engineering frame and its relationship to the spacecraft clock; ground processing for and basic uses of the telemetry; the various message types used to transmit commands to the spacecraft; and the generation processes for the command message types.

Erickson, James K.↗
NASA NTRS2012

Sample-Clock Phase-Control Feedback

To demodulate a communication signal, a receiver must recover and synchronize to the symbol timing of a received waveform. In a system that utilizes digital sampling, the fidelity of synchronization is limited by the time between the symbol boundary and closest sample time location. To reduce this error, one typically uses a sample clock in excess of the symbol rate in order to provide multiple samples per symbol, thereby lowering the error limit to a fraction of a symbol time. For systems with a large modulation bandwidth, the required sample clock rate is prohibitive due to current technological barriers and processing complexity. With precise control of the phase of the sample clock, one can sample the received signal at times arbitrarily close to the symbol boundary, thus obviating the need, from a synchronization perspective, for multiple samples per symbol. Sample-clock phase-control feedback was developed for use in the demodulation of an optical communication signal, where multi-GHz modulation bandwidths would require prohibitively large sample clock frequencies for rates in excess of the symbol rate. A custom mixedsignal (RF/digital) offset phase-locked loop circuit was developed to control the phase of the 6.4-GHz clock that samples the photon-counting detector output. The offset phase-locked loop is driven by a feedback mechanism that continuously corrects for variation in the symbol time due to motion between the transmitter and receiver as well as oscillator instability. This innovation will allow significant improvements in receiver throughput; for example, the throughput of a pulse-position modulation (PPM) with 16 slots can increase from 188 Mb/s to 1.5 Gb/s.

Quirk, Kevin J.↗
DOE OSTI2024

Beam Synchronous for the Rest of Us!

Fermilab’s Tevatron Clock (TCLK) infrastructure has been an integral part of the accelerator control network since the 1980’s. This 10MHz Manchester encoded protocol has enabled flexible, real-time event distribution for thousands of devices connected to the timing network with a high degree of reliability. Forthcoming upgrades to the Fermilab complex (PIP-II, LBNF, ACORN) necessitate higher levels of precision to maintain inter-bunch timing for Instrumentation and Control purposes. This presents as an opportunity to refine the event distribution protocol for tighter synchronization between machines, experiments, and eventually far-site operations. This paper outlines a method by which beam-synchronous events may be distributed through asynchronous serial protocols via integration with local LLRF and global PPS reference signals. This method is ideal for synchrotron machines with aggressive frequency sweeps (such as Fermilab's 38~53MHz Booster) and allows for precision timing to be maintained across machines without specialized hardware.

43 PARTICLE ACCELERATORS↗
DOE OSTI2025

In-orbit operation of Resolve Filter Wheel and modulated X-ray source

The Resolve soft X-ray spectrometer is a high spectral resolution microcalorimeter spectrometer for the X-ray Imaging and Spectroscopy Mission. In the beam of Resolve, there is a filter wheel containing X-ray filters. In the beam, there is also an active calibration source, the modulated X-ray source (MXS), which can provide pulsed X-rays to facilitate gain calibration. The filter wheel consists of six filter positions. Two open positions, one 55 Fe source to aid in spectrometer characterization during the commissioning phase, and three transmission filters: a neutral density filter, an optical blocking filter, and a beryllium filter. The X-ray intensity, pulse period, and pulse separation of an MXS are highly configurable. Furthermore, the switch-on time is synchronized with the spacecraft’s internal clock to give accurate start and end times of the pulses. One of the issues raised during ground testing was the susceptibility of an MXS at high voltage to ambient light. Although measures were taken to mitigate the light leak, the efficacy of those measures must be verified in orbit. Along with an overview of issues raised during ground testing, we will discuss the calibration source and the filter performance in-flight and compare with the transmission curves present in the Resolve calibration database.

X-ray Imaging and Spectroscopy Mission/Resolve↗
DOE OSTI2026

LuSEE-night power distribution system design

The Lunar Surface Electromagnetic Experiment at Night (LuSEE-Night) is a low-frequency, 0.5 to 50 MHz, radio experiment on the radio-quiet far side of the Moon. The instrument will be launched by NASA Commercial Lunar Payload Services in 2026. The LuSEE-Night instrument core is composed of a radio frequency spectrometer (SPT) processing signals from four antennas, the Data Controller Board (DCB), low electromagnetic interference (EMI) Picket Fence Power Supply (PFPS), and Power Distribution Unit (PDU). The battery powers the instrument during the lunar night and stores energy harvested by the solar panel array during the lunar day. The battery charging is controlled by the Power Conditioning and Distribution Unit (PCDU). The unregulated power is supplied either by the SpaceCraft (S/C) or the battery and gets distributed to the PFPS, communication radio, heaters, and deployables through the PDU. The PFPS generates all regulated low-voltage rails using switching regulation synchronized to the LuSEE-Night clock, which ensures self-generated EMI will be confined to well-defined frequency bins. Here, we discussed the unregulated power distribution system architecture and functionality. The PDU engineering and flight modules are developed and characterized to confirm compliance with LuSEE-Night requirements. At the time of writing, all power subsystem components have been integrated into the payload.

47 OTHER INSTRUMENTATION↗
NASA NTRS1976

Power spectra of sinusoidal amplitude-modulated binary signals

Power spectra for binary phase-shift keyed (PSK) and frequency-shift keyed (FSK) signals with combined sinusoidal amplitude modulation by the bit rate clock are presented. Such signal formats have application in 'burst' communication systems wherein reliable bit synchronization is provided with relative receiver simplicity. Effects of the clock amplitude modulation index and phase are considered, and corresponding power spectra are illustrated. Further, effects of the clock parameters on the rate of spectral rolloff are given and compared with those of conventional PSK and FSK spectra.

Gee, T. H.↗
NASA NTRS1989

Apparatus for using a time interval counter to measure frequency stability

An apparatus for measuring the relative stability of two signals is disclosed comprising a means for mixing the two signals down to a beat note sine wave and for producing a beat note square wave whose upcrossings are the same as the sine wave. A source of reference frequency is supplied to a clock divider and interval counter to synchronize them and to generate a picket fence for providing a time reference grid of period shorter than the beat period. An interval counter is employed to make a preliminary measurement between successive upcrossings of the beat note square wave for providing an approximate time interval therebetween as a reference. The beat note square wave and the picket fence are then provided to the interval counter to provide an output consisting of the time difference between the upcrossing of each beat note square wave cycle and the next picket fence pulse such that the counter is ready for each upcrossing and dead time is avoided. A computer containing an algorithm for calculating the exact times of the beat note upcrossings then computes the upcrossing times.

Greenhall, Charles A.↗
NASA NTRS1990

Verifying an interactive consistency circuit: A case study in the reuse of a verification technology

The work done at ORA for NASA-LRC in the design and formal verification of a hardware implementation of a scheme for attaining interactive consistency (byzantine agreement) among four microprocessors is presented in view graph form. The microprocessors used in the design are an updated version of a formally verified 32-bit, instruction-pipelined, RISC processor, MiniCayuga. The 4-processor system, which is designed under the assumption that the clocks of all the processors are synchronized, provides software control over the interactive consistency operation. Interactive consistency computation is supported as an explicit instruction on each of the microprocessors. An identical user program executing on each of the processors decides when and on what data interactive consistency must be performed. This exercise also served as a case study to investigate the effectiveness of reusing the technology which was developed during the MiniCayuga effort for verifying synchronous hardware designs. MiniCayuga was verified using the verification system Clio which was also developed at ORA. To assist in reusing this technology, a computer-aided specification and verification tool was developed. This tool specializes Clio to synchronous hardware designs and significantly reduces the tedium involved in verifying such designs. The tool is presented and how it was used to specify and verify the interactive consistency circuit is described.

Bickford, Mark↗
NASA NTRS1993

Plans to improve the experimental limit in the comparison of the east-west and west-east one-way light propagation times on the rotating earth

The preceding paper describes the results so far (interrupted in the Spring of 1989 because of lack of funds) of an experiment comparing the one-way light propagation times on the surface of the rotating Earth. For the 20 Km path length component in the East-West direction the predicted difference between the opposite sense propagation times would be 160 ps, if the approximately 360 Km/s surface speed of the Earth gives effective light speeds of 3 x 10(exp 8) m/s +/- 360 m/s. This could lead to a prediction of the difference between the clock transport and the light pulse synchronization methods described in the preceding paper: delta(T) = 0.5 (160) = 80 ps. The current upper bound of approximately 100 ps for delta(T) is limited by poorly understood systematic errors. The most important seems to be intensity-dependent time delays in the remote light pulse avalanche photo-diode detector. This will be replaced by a continuously operating circular scan streak camera having single photon sensitivity and a time resolution of approximately 5 ps. (This camera has recently been developed by the Xian Institute of Optics and Precision Mechanics in the P.R.C.). Better isolation from shocks and vibration for the Sigma-Tau hydrogen maser during transport will be provided. It is hoped that delta(T) is less than 20 ps can be achieved.

Alley, C. O.↗
NASA NTRS2011

STRS SpaceWire FPGA Module

An FPGA module leverages the previous work from Goddard Space Flight Center (GSFC) relating to NASA s Space Telecommunications Radio System (STRS) project. The STRS SpaceWire FPGA Module is written in the Verilog Register Transfer Level (RTL) language, and it encapsulates an unmodified GSFC core (which is written in VHDL). The module has the necessary inputs/outputs (I/Os) and parameters to integrate seamlessly with the SPARC I/O FPGA Interface module (also developed for the STRS operating environment, OE). Software running on the SPARC processor can access the configuration and status registers within the SpaceWire module. This allows software to control and monitor the SpaceWire functions, but it is also used to give software direct access to what is transmitted and received through the link. SpaceWire data characters can be sent/received through the software interface, as well as through the dedicated interface on the GSFC core. Similarly, SpaceWire time codes can be sent/received through the software interface or through a dedicated interface on the core. This innovation is designed for plug-and-play integration in the STRS OE. The SpaceWire module simplifies the interfaces to the GSFC core, and synchronizes all I/O to a single clock. An interrupt output (with optional masking) identifies time-sensitive events within the module. Test modes were added to allow internal loopback of the SpaceWire link and internal loopback of the client-side data interface.

Lux, James P.↗
NASA NTRS2013

Apparatus and Method for Compensating for Process, Voltage, and Temperature Variation of the Time Delay of a Digital Delay Line

A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Seefeldt, James↗
NASA NTRS2014

Centering a DDR Strobe in the Middle of a Data Packet

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Johnson, Michael↗
NASA NTRS1981

Cross-spectrum symbol synchronization

A popular method of symbol synchronization exploits one aspect of generalized harmonic analysis, normally referred to as the cross-spectrum. Utilizing nonlinear techniques, the input symbol energy is effectively concentrated onto multiples of the symbol clock frequency, facilitating application of conventional phase lock synchronization techniques. A general treatment of the cross-spectrum technique is developed and shown to be applicable across a broad class of symbol modulation formats. An important specific symbol synchronization application is then treated, focusing the general development to provide both insight and quantitative measure of the performance impact associated with variation in these key synchronization parameters: symbol modulation format, symbol transition probability, symbol energy to noise density ratio, and symbol rate to filter bandwidth ratio.

Mccallister, R. D.↗
NASA NTRS2009

Digital Synchronizer without Metastability

A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.

Simle, Robert M.↗
NASA NTRS2008

An Overview of Starfish: A Table-Centric Tool for Interactive Synthesis

Engineering is an interactive process that requires intelligent interaction at many levels. My thesis [1] advances an engineering discipline for high-level synthesis and architectural decomposition that integrates perspicuous representation, designer interaction, and mathematical rigor. Starfish, the software prototype for the design method, implements a table-centric transformation system for reorganizing control-dominated system expressions into high-level architectures. Based on the digital design derivation (DDD) system a designer-guided synthesis technique that applies correctness preserving transformations to synchronous data flow specifications expressed as co- recursive stream equations Starfish enhances user interaction and extends the reachable design space by incorporating four innovations: behavior tables, serialization tables, data refinement, and operator retiming. Behavior tables express systems of co-recursive stream equations as a table of guarded signal updates. Developers and users of the DDD system used manually constructed behavior tables to help them decide which transformations to apply and how to specify them. These design exercises produced several formally constructed hardware implementations: the FM9001 microprocessor, an SECD machine for evaluating LISP, and the SchemEngine, garbage collected machine for interpreting a byte-code representation of compiled Scheme programs. Bose and Tuna, two of DDD s developers, have subsequently commercialized the design derivation methodology at Derivation Systems, Inc. (DSI). DSI has formally derived and validated PCI bus interfaces and a Java byte-code processor; they further executed a contract to prototype SPIDER-NASA's ultra-reliable communications bus. To date, most derivations from DDD and DRS have targeted hardware due to its synchronous design paradigm. However, Starfish expressions are independent of the synchronization mechanism; there is no commitment to hardware or globally broadcast clocks. Though software back-ends for design derivation are limited to the DDD stream-interpreter, targeting synchronous or real-time software is not substantively different from targeting hardware.

Tsow, Alex↗
NASA NTRS2007

Gravity Probe B Timing System and Roll Phase Determination

An oven-controlled crystal oscillator at 16.368 MHz provides clock signals to all GP-B components and synchronizes the data collection, transmission and processing. The sampled science data signals are stamped with the vehicle time, a counter of the 10Hz data strobe divided down from the clock. The GPS receiver supplies an external reference for time transfer between the vehicle time and coordinated universal time. Ground and space flight tests show the time transfer error is within 1 microsecond. The time latency between the effective sample time of science signals and the stamped vehicle time is verified to 1 ms in the ground tests. The GP-B satellite is controlled to roll with a period of 77.5 sec about an axis along the direction to the guide star to average out the disturbance torques fixed to the body of the satellite and reduce the gyroscope readout noise. The roll phase is determined on the ground to high accuracy with the telemetry data from two star trackers and used in the data analysis to separate the drifts of gyroscope spin axes in the orbital plane and perpendicular to the orbital plane. The flight data shows that the roll phase is controlled to within 40 arcsec with a measurement uncertainty of 7 arcsec.

Jie, Li↗
NASA NTRS1973

Television multiplexing system

A television multiplexing system which includes a circuit that inserts a digital codes sync signal and a digital code into a video signal for identifying the channel is described. The digital sync signal and the digital coded signals are generated by a single crystal controlled clock so that they are always in synchronism with each other. In demultiplexing the signals are utilized for shifting the digital coded signals into a shift register. The shift register, in turn, activates a decoder according to the code stored in the shift register for selecting the proper recording disk or receiver for storing the video signal.

Simpkins, L. G.↗
NASA NTRS1972

Precision geodesy via radio interferometry.

Very-long-baseline interferometry experiments, involving observations of extragalactic radio sources, were performed in 1969 to determine the vector separations between antenna sites in Massachusetts and West Virginia. The 845.130-kilometer baseline was estimated from two separate experiments. The results agreed with each other to within 2 meters in all three components and with a special geodetic survey to within 2 meters in length; the differences in baseline direction as determined by the survey and by interferometry corresponded to discrepancies of about 5 meters. The experiments also yielded positions for nine extragalactic radio sources and allowed the hydrogen maser clocks at the two sites to be synchronized.

Hinteregger, H. F.↗