SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Random-fault densities measured in array of standard structures. Test pattern is array of standard circuit elements built into circuit chip along with, or in lieu of, integrated circuit objective process. Measurements on ray made and interpreted so fabrication process can be corrected as necessary.
Aluminized plastic protects integrated circuits from static discharge. Snap-on cover shorts leads of integrated-circuit flatpack to prevent damage from electrostatic discharges during transport, installation, or other handling before final testing. Cover removed only during lead bending and testing.
Widths and spacings of conductor lines on integrated circuits measured electrically by split cross-bridge resistor technique. Speeds evaluation of integrated-circuit fabrication processes. When measurement of probe currents and voltages and reduction of measurement data automated, test structure probed and characterized in less than one second.
A number of fixturing techniques compatible with automatic network analysis are presented. The fixtures are capable of characterizing GaAs Monolithic Microwave Integrated Circuits (MMICs) at K and Ka band. Several different transitions are used to couple the RF test port to microstrip. Fixtures which provide chip level de-embedding are included. In addition, two advanced characterization techniques are assessed.
The results of an experiment to test storage effects on electric cells of a battery are presented and discussed. The type of cells were the 20 amp-hour OAO type. The various modes that were tested were the integration type mode, the trickle charge, the discharge shorted and the discharged OCV (open current voltage). Every six months the cells were reconditioned and approximately two weeks of tests were performed. The tests included three capacity checks, two zero-degree overcharge tests and an internal short test (the cells are shunted for 16 hours, the shunt removed and allowed to stand on local circuit recovery for 24 hours). The integration pack was discontinued after three years and the trickle charge shorted packs after five years.
The comb/serpentine/cross-bridge structure was developed to monitor and evaluate same layer shorts and step coverage problems (open and high-resistance wire over steps) for integrated circuit fabrication processes. The cross-bridge provides local measurements of wire sheet resistance and wirewidth. These local parametric measurements are used in the analysis of the serpentine wire, which identifies step coverage problems. The comb/serpentine/cross-bridge structure was fabricated with 3 microns CMOS/bulk p-well process and tested using a computer-controlled parametric test system.
We present here the design, development and test of an integrated sub-millimeter front-end featuring a 520-600 GHz sub-harmonic mixer and a 260-300 GHz frequency tripler in a single cavity. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional machined as well as silicon micro-machined blocks. Measurement results on the metal block give best DSB mixer noise temperature of 2360 K and conversion losses of 7.7 dB at 520 GHz. Preliminary results on the silicon micro-machined blocks give a DSB mixer noise temperature of 4860 K and conversion losses of 12.16 dB at 540 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer for both packages is between 30 and 50 mW
The fabrication techniques and detail procedures for creating P-channel Metal-Oxide-Semiconductor (P-MOS) integrated circuits at George C. Marshall Space Flight Center (MSFC) are described. Examples of P-MOS integrated circuits fabricated at MSFC together with functional descriptions of each are given. Typical electrical characteristics of high and low threshold P-MOS discrete devices under given conditions are provided. A general description of MSFC design, mask making, packaging, and testing procedures is included. The capabilities described in this report are being utilized in: (1) research and development of new technology, (2) education of individuals in the various disciplines and technologies of the field of microelectronics, and (3) fabrication of many types of specially designed integrated circuits which are not commercially feasible in small quantities for in-house research and development programs.
Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed.
Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.
Integrated optic waveguide circuits with a phase bias and modulator on the same chip were designed, fabricated, and tested for use in a fiber-optic rotation sensor (gyro) under development. Single mode fiber-optic pigtails were permanently coupled to the four ports of the chip. The switch format was based on coherent coupling between waveguides formed in Z-cut LiNbO3. The control of the coupling was achieved by electro-optically varying the phase propagation constants of each guide. Fiber-to-chip interfacing required the development of appropriate fixturing and manipulation techniques to achieve the close tolerance needed for high coupling efficiency between a fiber with an approximately 5 micron m core and a channel guide with a roughly 2 micron m by 5 micron m cross section. Switch and chip performance at 0.85 micron m is discussed as well as potential improvements related to insertion loss reduction, switching voltages, and suppression of Li2O out-diffusion.
Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.
A NASA-wide team, funded under the NASA Electronic Parts and Packaging Program (NEPP), was formed to collaborate and to establish reliability of various electronic parts/packaging and assemblies for operation under extreme cold temperatures. One of the primary objectives of the NEPP is to expedite the infusion of cutting edge technologies into the present and future NASA missions. Commercial-off-the-shelf (COTS) emerging electronic parts/packages due to their lower weight, increased functionality, and lower cost are excellent candidates for space missions if they are characterized to show that they will meet the stringent reliability and quality requirements. Characterizations, especially for the extreme cold temperatures, are required since very limited data are available by manufacturers or users. For severe military environments, the temperature conditions to -65 C are the lowest temperature for which these parts/packages and assemblies are qualified. New data beyond this relatively benign cold temperature are required for numerous NASA missions. Several parts/packages, based on the project recommendation for their immediate and future needs, were selected for detailed characterization to cold temperature regimes down to liquid nitrogen (-196 C), covering both Mars cold temperature (-125 C) and asteroid (- 180 C) lander environmental requirements. Numerous parts/packages and assemblies were characterized during extreme temperature environmental tests. Several electrical parameters were characterized at discrete temperatures to -185 C to determine if they remain within their specification ranges. Both packages and circuit boards were subjected to nondestructive testing including optical, X-ray, and acoustic microscopy to document their integrity prior to environment exposure. Package/board assemblies were also subjected to X-ray to characterize solder joint integrity including void levels. Both parts and assemblies were subjected to thermal cycling with a large temperature swing enveloping numerous NASA missions. Details of the performed tests and the results obtained are presented.
Space radiation damage and proton induced transient effects were evaluated on 4.4 μm cutoff HgCdTe avalanche photodiode (APD) arrays developed by Leonardo DRS. Device performances as a function of total dose up to 100 krad (Si) were measured with ~60 MeV protons on 3 types of APD samples: 4x4 pixel APD fanout arrays with and without connection to a read-out integrated circuit (ROIC), and a 2x8 pixel photon counting APD focal plane array (FPA). A gamma-ray test was also conducted to study ionization effects. Both APD arrays exhibited a small decrease in the quantum efficiency and a linear increase in the dark current with the proton fluence. The 2x8 pixel photon counting FPA also exhibited an increase in the dark count rate with proton dose. After the proton irradiation and an overnight room temperature warm-up, the APD dark currents at 80 K increased significantly in both types of APD arrays. All radiation damage to these HgCdTe APD arrays annealed out after baking them at >85 °C for several hours. Transient protons through the devices were found to cause large pulses at the detector output but recover within 1 μs.
The key to implementing self-diagnosing design is a systems engineering task focused on design for testability concurrent with design for functionality. The design for testability process described here is the product of several years of DOD study and experience. Its application to the space station has begun on Work Package II under NASA and McDonnell direction. Other work package teams are being briefed by Harris Corporation with the hope of convincing them to embrace the process. For the purpose of this discussion the term testability is used to describe the systems engineering process by which designers can assure themselves and their reviewers that their designs are TESTABLE, that is they will support the downstream process of determining their functionality. Due to the complexity and density of present-day state-of-the-art designs, such as pipeline processors and high-speed integrated circuit technology, testability feature design is a critical requirement of the functional design process. A systematic approach to Space systems test and checkout as well as fault detection fault isolation reconfiguration (FDFIR) will minimize operational costs and maximize operational efficiency. An effective design for the testability program must be implemented by all contractors to insure meeting this objective. The process is well understood and technology is here to support it.
We have developed a range of techniques useful for constructing analog and digital circuits for operation in a liquid Helium environment (4.2K), using commercially available low power components. The challenges encountered in designing cryogenic electronics include finding components that can function usefully in the cold and possess low enough power dissipation so as not to heat the systems they are designed to measure. From design, test, and integration perspectives it is useful for components to operate similarly at room and cryogenic temperatures; however this is not a necessity. Some of the circuits presented here have been used successfully in the MUSTANG and in the GISMO camera to build a complete digital to analog multiplexer (which will be referred to as the Cryogenic Address Driver board). Many of the circuit elements described are of a more general nature rather than specific to the Cryogenic Address Driver board, and were studied as a part of a more comprehensive approach to addressing a larger set of cryogenic electronic needs.
A CMOS Process Monitor, consisting of eight basic test structures, has been prepared to acquire key CMOS parameters to assist in VLSI wafer acceptance. The test structures can be probed using a 2 by N probe pad array and can be arranged to fit into either the interior or the scribe lane of an integrated circuit chip. In order to facilitate the general use of the monitor, a document is being prepared that describes its design, layout, measurement, and analysis. This paper describes the structures included in the monitor, the methodology used to create the monitor, and test results from the monitor.
Experimentally, thermal annealing is known to be a factor which enables a number of different integrated circuits (IC's) to recover their operating characteristics after suffering radiation damage in the space radiation environment; thus, decreasing and limiting long term cumulative total-dose effects. This annealing is also known to be accelerated at elevated temperatures both during and after irradiation. Linear response theory (LRT) was applied, and a linear response function (LRF) to predict the radiation/annealing response of sensitive parameters of IC's for long term (several months or years) exposure to the space radiation environment were constructed. Compressing the annealing process from several years in orbit to just a few hours or days in the laboratory is achieved by subjecting the IC to elevated temperatures or by increasing the typical spaceflight dose rate by several orders of magnitude for simultaneous radiation/annealing only. The accomplishments are as follows: (1) the test procedure to make predictions of the radiation response was developed; (2) the calculation of the shift in the threshold potential due to the charge distribution in the oxide was written; (3) electron tunneling processes from the bulk Si to the oxide region in an MOS IC were estimated; (4) in order to connect the experimental annealing data to the theoretical model, constants of the model of the basic annealing process were established; (5) experimental data obtained at elevated temperatures were analyzed; (6) time compression and reliability of predictions for the long term region were shown; (7) a method to compress test time and to make predictions of response for the nonlinear region was proposed; and (8) nonlinearity of the LRF with respect to log(t) was calculated theoretically from a model.