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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16

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NASA NTRS1981

Design, development, and field demonstration of a remotely deployable water quality monitoring system

A prototype water quality monitoring system is described which offers almost continuous in situ monitoring. The two-man portable system features: (1) a microprocessor controlled central processing unit which allows preprogrammed sampling schedules and reprogramming in situ; (2) a subsurface unit for multiple depth capability and security from vandalism; (3) an acoustic data link for communications between the subsurface unit and the surface control unit; (4) eight water quality parameter sensors; (5) a nonvolatile magnetic bubble memory which prevents data loss in the event of power interruption; (6) a rechargeable power supply sufficient for 2 weeks of unattended operation; (7) a water sampler which can collect samples for laboratory analysis; (8) data output in direct engineering units on printed tape or through a computer compatible link; (9) internal electronic calibration eliminating external sensor adjustment; and (10) acoustic location and recovery systems. Data obtained in Saginaw Bay, Lake Huron are tabulated.

Wallace, J. W.↗

NASA NTRS1983

Application experience with the NASA aircraft interrogation and display system - A ground-support equipment for digital flight systems

The NASA Dryden Flight Research Facility has developed a microprocessor-based, user-programmable, general-purpose aircraft interrogation and display system (AIDS). The hardware and software of this ground-support equipment have been designed to permit diverse applications in support of aircraft digital flight-control systems and simulation facilities. AIDS is often employed to provide engineering-units display of internal digital system parameters during development and qualification testing. Such visibility into the system under test has proved to be a key element in the final qualification testing of aircraft digital flight-control systems. Three first-generation 8-bit units are now in service in support of several research aircraft projects, and user acceptance has been high. A second-generation design, extended AIDS (XAIDS), incorporating multiple 16-bit processors, is now being developed to support the forward swept wing aircraft project (X-29A). This paper outlines the AIDS concept, summarizes AIDS operational experience, and describes the planned XAIDS design and mechanization.

Glover, R. D.↗

NASA NTRS1985

A star camera aspect system suitable for use in balloon experiments

A balloon-borne experiment containing a star camera aspect system was designed, built, and flown. This system was designed to provide offset corrections to the magnetometer and inclinometer readings used to control an azimuth and elevation pointed experiment. The camera is controlled by a microprocessor, including commendable exposure and noise rejection threshold, as well as formatting the data for telemetry to the ground. As a background program, the microprocessor runs the aspect program to analyze a fraction of the pictures taken so that aspect information and offset corrections are available to the experiment in near real time. The analysis consists of pattern recognition of the star field with a star catalog in ROM memory and a least squares calculation. The performance of this system in ground based tests is described. It is part of the NASA/GSFC High Energy Gamma-Ray Balloon Instrument (2).

Hunter, S. D.↗

NASA NTRS1986

Design, construction, activation, and operation of a high intensity acoustic test chamber

The design philosophy, construction, integration, and activation of the high intensity acoustic test chamber for production acceptance testing of satellites are discussed. The 32,000 cubic-foot acoustic test cell consists of a steel reinforced concrete chamber with six electropneumatic noise generators. One of the innovative features of the chamber is a unique quarter horn assembly that acoustically couples the noise generators to the chamber. Design concepts, model testing, and evaluation results are presented. Considerations such as nitrogen versus compressed air source, digital closed loop spectrum control versus manual equalizers, and microprocessor based interlock systems are included. Construction difficulties, anomalies encountered, and their resolution are also discussed. Results of the readiness testing are highlighted.

Kamel, L. T.↗

NASA NTRS1990

The status of cesium beam frequency standards

There has been a lot of progress in cesium beam frequency standards in the last few years some of which will be reported here. Optical pumping is being pursued actively in a number of laboratories. Optically slowed and cooled beams have been demonstrated as well as traps for cold neutral atoms. The microwave cavity performance with regard to local phase shift at the beam holes was improved by use of carefully designed and built ring structures for the cavity ends. Work is being done on improvements in electronics with some emphasis on use of digital circuitry and microprocessors. The frequency pulling due to microwave Delta M = +/- 1 transitions (Ramsey pulling) was analyzed and shown to be important. Status of cesium beam frequency standards in some of the laboratories as well as some of the commercial work is discussed. Optical pumping and detection are discussed.

Cutler, Leonard S.↗

NASA NTRS1993

California Student Get Away Special Payload GAS-450

The California Student Get Away Special Payload GAS-450, recently went into orbit on the STS-57 Mission, Space Shuttle, Endeavour, 21 June 1993, 6:14 AM and landed on the 29 June 1993 at Kennedy Space Center (KSC). Fifty students from 13 California Central Coast Schools and one in San Francisco designed and built 13 active experiments (6 modules) for this mission. Preliminary analysis of our completely reusable payload bus system indicated that the structure, power system, microprocessor, and sensor systems in each experiment module worked flawlessly. The experiments themselves performed exceptionally well with a 60 percent success ratio. The students are thoroughly documenting their own experiments and results via a standard research paper guideline generated by the GAS-450 technical staff. Lessons learned (program management and technical) are documented at the end of the paper. If any other organization needs payload/experiment development or NASA documentation assistance, then please contact us. We can help make your idea a space tested reality. Three years of intense effort culminated on 3 February 1993, the GSFC field operations team at Kennedy Space Center performed the final pressure decay and electrical tests upon the fully integrated GAS-450 flight canister. Subsequently, the payload was integrated with its parent GAS Bridge Assembly in mid-February and the bridge was transferred to the KSC orbiter team in late February 1993. The STS-57 mission originally scheduled to launch on the 29 April 1993 slipped until 21 June 1993. Our Payload shared the cargo bay with ten other GAS Canisters, the EUREKA experiment, the SHOOT experiment, and the SPACEHAB-1 module. The SIL technical staff retrieved the GAS-450 payload after flight from the NASA Spin Test Facility at KSC and shipped it back to California on the 22 July 1993 for student analysis at Allan Hancock College this summer.

Ray, Glen↗

NASA NTRS1980

An experimental distributed microprocessor implementation with a shared memory communications and control medium

The distributed processing concept is defined in terms of control primitives, variables, and structures and their use in performing a decomposed discrete Fourier transform (DET) application function. The design assumes interprocessor communications to be anonymous. In this scheme, all processors can access an entire common database by employing control primitives. Access to selected areas within the common database is random, enforced by a hardware lock, and determined by task and subtask pointers. This enables the number of processors to be varied in the configuration without any modifications to the control structure. Decompositional elements of the DFT application function in terms of tasks and subtasks are also described. The experimental hardware configuration consists of IMSAI 8080 chassis which are independent, 8 bit microcomputer units. These chassis are linked together to form a multiple processing system by means of a shared memory facility. This facility consists of hardware which provides a bus structure to enable up to six microcomputers to be interconnected. It provides polling and arbitration logic so that only one processor has access to shared memory at any one time.

Mejzak, R. S.↗

NASA NTRS1997

An Assessment of a Beowulf System for a Wide Class of Analysis and Design Software

A typical Beowulf system, such as the machine at the Jet Propulsion Laboratory (JPL), may comprise 16 nodes interconnected by 100 base T Fast Ethernet. Each node may include a single Inter Pentium Pro 200 MHz microprocessor, 128 MBytes of DRAM, 2.5 GBytes of IDE disk, and PCI bus backplane, and an assortment of other devices.

Beowulf System↗

NASA NTRS1981

NASA Communications Division (NASCOM) Tracking and Data Relay Satellite System (TDRSS) shuttle multiplexer-demultiplexer data system (MDM) and supporting items

The multiplexer-demultiplexer (MDM) project included the design, documentation, manufacture, and testing of three MDM Data Systems. The equipment is contained in 59 racks, and includes more than 3,000 circuit boards and 600 microprocessors. Spares, circuit card testers, a master set of programmable integrated circuits, and a program development system were included as deliverables. All three MDM's were installed, and were operationally tested. The systems performed well with no major problems. The progress and problems analysis, addresses schedule conformance, new technology, items awaiting government approval, and project conclusions are summarized. All contract modifications are described.

New, S. R.↗

NASA NTRS1984

Nickel Cadmium Charge Control Concepts

The design and testing of charge control concepts for several power systems is presented. The design of the CRAM charge control system for the SAS satellites and the design of the battery charge regulator for the AMPTE satellites is reviewed. Another charge control concept examined is for the OPEN program and its use of a microprocessor. The use of the voltage limiter is also discussed.

Sullivan, R. M.↗

NASA NTRS2011

MicroShell Minimalist Shell for Xilinx Microprocessors

MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is discovered in a routine but the system cannot be rebooted: Shell allows a skilled operator to directly edit the binary executable in memory. With some forethought, MicroShell code can be located in a different memory location from custom code, permitting the custom functionality to be overwritten at any time without stopping the controlling shell.

Werne, Thomas A.↗

NASA NTRS2016

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally approx.300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.

data acquisition↗

NASA NTRS1986

Investigation of an advanced fault tolerant integrated avionics system

Presented is an advanced, fault-tolerant multiprocessor avionics architecture as could be employed in an advanced rotorcraft such as LHX. The processor structure is designed to interface with existing digital avionics systems and concepts including the Army Digital Avionics System (ADAS) cockpit/display system, navaid and communications suites, integrated sensing suite, and the Advanced Digital Optical Control System (ADOCS). The report defines mission, maintenance and safety-of-flight reliability goals as might be expected for an operational LHX aircraft. Based on use of a modular, compact (16-bit) microprocessor card family, results of a preliminary study examining simplex, dual and standby-sparing architectures is presented. Given the stated constraints, it is shown that the dual architecture is best suited to meet reliability goals with minimum hardware and software overhead. The report presents hardware and software design considerations for realizing the architecture including redundancy management requirements and techniques as well as verification and validation needs and methods.

Dunn, W. R.↗

NASA NTRS1978

A study of standard building blocks for the design of fault-tolerant distributed computer systems

This paper presents the results of a study that has established a standard set of four semiconductor VLSI building-block circuits. These circuits can be assembled with off-the-shelf microprocessors and semiconductor memory modules into fault-tolerant distributed computer configurations. The resulting multi-computer architecture uses self-checking computer modules backed up by a limited number of spares. A redundant bus system is employed for communication between computer modules.

Rennels, D. A.↗

NASA NTRS1981

Wide field of view laser beacon system for three-dimensional aircraft position measurement

This paper presents a new wide field of view laser beacon system for measurement, in three dimensions, of aircraft or other remote objects. The system is developed for aircraft collision hazard warning independent of ground-based hardware, as well as for flight research, helicopter-assisted construction and rescue, and robotic manipulation applications. Accurate information describing the relative range, elevation, and azimuth of the aircraft are generated by the sweep of a low-power fan-shaped rotating laser beacon past an array of optical detectors. The system achieves a wide angle of acceptance of laser beacon light through use of compound parabolic concentrators, which collimate the light for spectral filtering to minimize solar interference. An on-board microprocessor system converts the pulse sequence to aircraft position in real time. System reliability and performance are enhanced through narrow pass filtering of the pulse signals, digital logic design to mask spurious signals, and adaptive modulation of trigger threshold levels.

Sweet, L. M.↗

NASA NTRS1983

ADA and multi-microprocessor real-time simulation

The selection of a high-order programming language for a real-time distributed network simulation is described. The additional problem of implementing a language on a possibly changing network is addressed. The recently designed language ADA (trademarked by DoD) was chosen since it provides the best model of the underlying application to be simulated.

Feyock, S.↗

NASA NTRS1984

Preprototype SAWD subsystem

A regenerable, three man preprototype solid amine, water desorbed (SAWD) CO2 removal and concentation subsystem was designed, fabricated, and successfully acceptance tested by Hamilton Standard. The preprototype SAWD incorporates a single solid amine canister to perform the CO2 removal function, an accumulator to provide the CO2 storage and delivery function, and a microprocessor which automatically controls the subsystem sequential operation and performance. The SAWD subsystem was configured to have a CO2 removal and CO2 delivery capability at the rate of 0.12 kg/hr (0.264 lb/hr) over the relative humidity range of 35 to 70%. The controller was developed to provide fully automatic control over the relative humidity range via custom software that was generated specifically for the SAWD subsystem. The preprototype SAWD subsystem demonstrated a total of 281 hours (208) cycles of operation during ten acceptance tests that were conducted over the 3 to 70% relative humidity range. This operation was comprised of 178 hours (128 cycles) in the CO2 overboard mode and 103 hours (80 cycles) in the CO2 reduction mode. The average CO2 removal/delivery rate met or exceeded the design specification rate of 0.12 kg/hr (0.254 lb/hr) for all ten of the acceptance tests.

Nalette, T. A.↗

NASA NTRS1995

The scheme machine: A case study in progress in design derivation at system levels

The Scheme Machine is one of several design projects of the Digital Design Derivation group at Indiana University. It differs from the other projects in its focus on issues of system design and its connection to surrounding research in programming language semantics, compiler construction, and programming methodology underway at Indiana and elsewhere. The genesis of the project dates to the early 1980's, when digital design derivation research branched from the surrounding research effort in programming languages. Both branches have continued to develop in parallel, with this particular project serving as a bridge. However, by 1990 there remained little real interaction between the branches and recently we have undertaken to reintegrate them. On the software side, researchers have refined a mathematically rigorous (but not mechanized) treatment starting with the fully abstract semantic definition of Scheme and resulting in an efficient implementation consisting of a compiler and virtual machine model, the latter typically realized with a general purpose microprocessor. The derivation includes a number of sophisticated factorizations and representations and is also deep example of the underlying engineering methodology. The hardware research has created a mechanized algebra supporting the tedious and massive transformations often seen at lower levels of design. This work has progressed to the point that large scale devices, such as processors, can be derived from first-order finite state machine specifications. This is roughly where the language oriented research stops; thus, together, the two efforts establish a thread from the highest levels of abstract specification to detailed digital implementation. The Scheme Machine project challenges hardware derivation research in several ways, although the individual components of the system are of a similar scale to those we have worked with before. The machine has a custom dual-ported memory to support garbage collection. It consists of four tightly coupled processes--processor, collector, allocator, memory--with a very non-trivial synchronization relationship. Finally, there are deep issues of representation for the run-time objects of a symbolic processing language. The research centers on verification through integrated formal reasoning systems, but is also involved with modeling and prototyping environments. Since the derivation algebra is basd on an executable modeling language, there is opportunity to incorporate design animation in the design process. We are looking for ways to move smoothly and incrementally from executable specifications into hardware realization. For example, we can run the garbage collector specification, a Scheme program, directly against the physical memory prototype, and similarly, the instruction processor model against the heap implementation.

Johnson, Steven D.↗