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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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275 records · Page 16
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NASA NTRS1989

Solitosynthesis: Cosmological evolution of non-topological solitons

The thermal creation, fusion, evaporation, and destruction of non-topological solitons (NTS) after a phase transition in the early universe is considered. By defining and following NTS statistical equilibrium and departures from it, and depending on particle physics parameters, one of three possible scenarios occurs. If reaction rates are high enough, a period of equilibrium occurs and relic abundances are determined by the freeze-out temperature. Equilibrium first drives most NTS's into their constituents (free phi particles) and then causes rapid fusion into large NTS's. If freeze-out occurs during the first phase, the NTS's are almost entirely destroyed, while if it occurs during the second phase, solitosynthesis occurs and NTS's may be cosmically relevant. For slow reaction rates the NTS's are born frozen out and have the abundance determined by the phase transition. Analytic approximations for determining the abundances are developed, and tested by numerically integrating a reaction network in an expanding universe. Unfortunately, for most of the parameter space considered, solito-destruction/evaporation occurs.

Griest, Kim↗
NASA NTRS2011

NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions

A paper discusses NEXUS, a common, next-generation avionics interconnect that is transparently compatible with wired, fiber-optic, and RF physical layers; provides a flexible, scalable, packet switched topology; is fault-tolerant with sub-microsecond detection/recovery latency; has scalable bandwidth from 1 Kbps to 10 Gbps; has guaranteed real-time determinism with sub-microsecond latency/jitter; has built-in testability; features low power consumption (< 100 mW per Gbps); is lightweight with about a 5,000-logic-gate footprint; and is implemented in a small Bus Interface Unit (BIU) with reconfigurable back-end providing interface to legacy subsystems. NEXUS enhances a commercial interconnect standard, Serial RapidIO, to meet avionics interconnect requirements without breaking the standard. This unified interconnect technology can be used to meet performance, power, size, and reliability requirements of all ranges of equipment, sensors, and actuators at chip-to-chip, board-to-board, or box-to-box boundary. Early results from in-house modeling activity of Serial RapidIO using VisualSim indicate that the use of a switched, high-performance avionics network will provide a quantum leap in spacecraft onboard science and autonomy capability for science and exploration missions.

He, Yutao↗
NASA NTRS2022

The Sun Radio Interferometer Space Experiment (SunRISE) Mission

The Sun Radio Interferometer Space Experiment (SunRISE) will provide an entirely new view on particle acceleration and transport in the inner heliosphere by creating the first low radio frequency interferometer in space to localize heliospheric radio emissions. By imaging and determining the location of decametric-hectometric (DH, 0.1 MHz–23 MHz) solar radio bursts, SunRISE will provide key information on particle acceleration mechanisms associated with coronal mass ejections (CMEs) and the magnetic field topology from active regions into interplanetary space. The SunRISE Observatory will consist of six space vehicles in a passive formation, in orbits designed to keep them within approximately 10 km of each other, and flying in a supersynchronous geosynchronous Earth orbit (GEO). Each space vehicle consists of a Solar DH-GNSS payload and a 6U form factor spacecraft. The SunRISE Observatory together with significant ground-based processing, will enable imaging of the Sun in a portion of the spectrum that is blocked by the ionosphere and cannot be observed from Earth. Key aspects that enable this mission are that only position knowledge of the space vehicles is required, not active control, and that the architecture involves a modest amount of on-board processing coupled with significant ground-based processing for navigation, position determination, and science operations. Mission-enabling advances in software-defined radios, GPS navigation and timing, and small spacecraft technologies, developed and flown on the DARPA High Frequency Research (DHFR) and the Community Initiative for Continuing Earth Radio Occultation (CICERO) have made this mission affordable and low-risk. The SunRISE mission will exploit the multiple spacecraft per aperture (MSPA) capability of NASA’s Deep Space Network (DSN), for more efficient data transfers of larger data volumes, and utilize commercial access to space, in which the SunRISE space vehicles will be carried to their target orbit as secondary payloads in conjunction with a larger host spacecraft intended for GEO.

Neilson, Tim↗
NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗
NASA NTRS2000

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency issues in the GA, it is possible to have idle processors. However, as long as the load at each processing node is similar, the processors are kept busy nearly all of the time. In applying GAs to circuit design, a suitable genetic representation 'is that of a circuit-construction program. We discuss one such circuit-construction programming language and show how evolution can generate useful analog circuit designs. This language has the desirable property that virtually all sets of combinations of primitives result in valid circuit graphs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. For example, a figure shows an 85 dB amplifier design evolved by our system, and another figure shows the performance of that circuit (gain and frequency response). In all tasks, our system is able to generate circuits that achieve the target specifications.

Long, Jason D.↗