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At least 307 records · Page 17

The BLAZE language - A parallel language for scientific programming

A Pascal-like scientific programming language, BLAZE, is described. BLAZE contains array arithmetic, forall loops, and APL-style accumulation operators, which allow natural expression of fine grained parallelism. It also employs an applicative or functional procedure invocation mechanism, which makes it easy for compilers to extract coarse grained parallelism using machine specific program restructuring. Thus BLAZE should allow one to achieve highly parallel execution on multiprocessor architectures, while still providing the user with conceptually sequential control flow. A central goal in the design of BLAZE is portability across a broad range of parallel architectures. The multiple levels of parallelism present in BLAZE code, in principle, allow a compiler to extract the types of parallelism appropriate for the given architecture while neglecting the remainder. The features of BLAZE are described and it is shown how this language would be used in typical scientific programming.

Mehrotra, Piyush↗

A parallel Householder tridiagonalization stratagem using scattered square decomposition

The parallel stratagem in this paper uses scattered square decomposition, introduced by Fox (1985), for its data assignment and then exploits parallelism in the solution steps of the sequential Householder tridiagonalization algorithm. One may condense a real symmetric full matrix A of order n into a tridiagonal form by the stratagem in concurrent machines where N(=D-squared) processors are used. Expressions for efficiency and speedup are given for the evaluation of the stratagem. An alternative stratagem which requires less data transmission but more computations is also discussed. The results shown that the Householder method of tridiagonalization may be implemented on a concurrent machine efficiently by scattered square decomposition provided that the number of matrix elements contained in each processor is much larger than the number of processors of the concurrent machine, and the ratio of the time to transmit one data item from one processor to any other processor to the time to perform a floating-point arithmetic operation is small enough.

Chang, H. Y.↗

An algorithm for a generalization of the Richardson extrapolation process

The paper presents a recursive method, designated the W exp (m)-algorithm, for implementing a generalization of the Richardson extrapolation process. Compared to the direct solution of the linear sytems of equations defining the extrapolation procedure, this method requires a small number of arithmetic operations and very little storage. The technique is also applied to solve recursively the coefficient problem associated with the rational approximations obtained by applying a d-transformation to power series. In the course of development a new recursive algorithm for implementing a very general extrapolation procedure is introduced, for solving the same problem. A FORTRAN program for the W exp (m)-algorithm is also appended.

Ford, William F.↗

Directed band ratioing for the retention of perceptually-independent topographic expression in chromaticity-enhanced imagery

A band ratioing method is developed which directs the retention of topographic expression and albedo information so that they remain depicted as prominent variations in image intensity. Band data are adjusted so that ratio values for each surface material coherently increase with increasing pixel bispectral radiance for all three ratios of the color composite. The retained topographic expression and albedo information do not significantly distort the ratio-enhanced band-variant reflectance information, and the resultant images are similar to chromaticity-enhanced band composite images, but require only simple arithmetic processing steps.

Crippen, Robert E.↗

Eight-Bit-Slice GaAs General Processor Circuit

Novel GaAs 8-bit slice enables quick and efficient implementation of variety of fast GaAs digital systems ranging from central processing units of computers to special-purpose processors for communications and signal-processing applications. With GaAs 8-bit slice, designers quickly configure and test hearts of many digital systems that demand fast complex arithmetic, fast and sufficient register storage, efficient multiplexing and routing of data words, and ease of control.

Weissman, John↗

Optical Firmware

Data-processing system exploits high speeds inherent in optical elements. Instruction sets for different computer operations reside on different external memory chips. Laser diodes activated for each operation generate light, reflected by holographic optical element to designated receptors in arithmetic and logic unit. Pattern of light beams embodies instruction set at given instant. With potential ability to reprogram in real time, conceptual system applicable to task-driven programming or artificial intelligence.

Bergman, Larry A.↗

The CSM testbed matrix processors internal logic and dataflow descriptions

This report constitutes the final report for subtask 1 of Task 5 of NASA Contract NAS1-18444, Computational Structural Mechanics (CSM) Research. This report contains a detailed description of the coded workings of selected CSM Testbed matrix processors (i.e., TOPO, K, INV, SSOL) and of the arithmetic utility processor AUS. These processors and the current sparse matrix data structures are studied and documented. Items examined include: details of the data structures, interdependence of data structures, data-blocking logic in the data structures, processor data flow and architecture, and processor algorithmic logic flow.

Regelbrugge, Marc E.↗

Formally verifying Ada programs which use real number types

Formal verification is applied to programs which use real number arithmetic operations (mathematical programs). Formal verification of a program P consists of creating a mathematical model of F, stating the desired properties of P in a formal logical language, and proving that the mathematical model has the desired properties using a formal proof calculus. The development and verification of the mathematical model are discussed.

Sutherland, David↗

Initial application of CAP-TSD to wing flutter

The initial application of the CAP-TSD computer program for wing flutter analysis is presented. Computational Aeroelasticity Program - Transonic Small Disturbance (CAP-TSD) is based on an approximate factorization (AF) algorithm that is stable and efficient on supercomputers with vector arithmetic. CAP-TSD was used to calculate steady and unsteady pressures on wings and configurations at subsonic, transonic, and supersonic Mach numbers. However, the CAP-TSD code has been developed primarily for aeroelastic analysis. The initial efforts for validation of the aeroelastic analysis capability is presented. The initial applications include two series of symmetric, planar wing planforms. Well defined modal properties are available for these wings. In addition, transonic flutter boundaries are available for evaluation of the transonic capabilities of CAP-TSD.

Cunningham, Herbert J.↗

Transformation based endorsement systems

Evidential reasoning techniques classically represent support for a hypothesis by a numeric value or an evidential interval. The combination of support is performed by an arithmetic rule which often requires restrictions to be placed on the set of possibilities. These assumptions usually require the hypotheses to be exhausitive and mutually exclusive. Endorsement based classification systems represent support for the alternatives symbolically rather than numerically. A framework for constructing endorsement systems is presented in which transformations are defined to generate and update the knowledge base. The interaction of the knowledge base and transformations produces a non-monotonic reasoning system. Two endorsement based reasoning systems are presented to demonstrate the flexibility of the transformational approach for reasoning with ambiguous and inconsistent information.

Sudkamp, Thomas↗

Limitations on K-T mass extinction theories based upon the vertebrate record

Theories of extinction are only as good as the patterns of extinction that they purport to explain. Often such patterns are ignored. For the terminal Cretaceous events, different groups of organisms in different environments show different patterns of extinction that to date cannot be explained by a single causal mechanism. Several patterns of extinction (and/or preservational bias) can be observed for the various groups of vertebrates from the uppermost Cretaceous Hell Creek Formation and lower Paleocene Tullock Formation in eastern Montana. The taxonomic level at which the percentage of survivals (or extinctions) is calculated will have an effect upon the perception of faunal turnover. In addition to the better known mammals and better publicized dinosaurs, there are almost 60 additional species of reptiles, birds, amphibians, and fish in the HELL Creek Formation. Simple arithmetic suggests only 33 percent survival of these vertebrates from the Hell Creek Fm. into the Tullock Fm. A more critical examination of the data shows that almost all Hell Creek species not found in the Tullock are represented in one of the following categories; extremely rare forms, elasmobranch fish that underwent rapid speciation taxa that although not known or rare in the Tullock, are found elsewhere. Each of the categories is largely the result of the following biases: taphonomy, ecological differences, taxonomic artifact paleogeography. The two most important factors appear to be the possible taphonomic biases and the taxonomic artifacts. The extinction patterns among the vertebrates do not appear to be attributable to any single cause, catastrophic or otherwise.

Archibald, J. David↗

Alaska SAR Facility (ASF5) SAR Communications (SARCOM) Data Compression System

The real-time operational requirements for SARCOM translation into a high speed image data handler and processor to achieve the desired compression ratios and the selection of a suitable image data compression technique with as low as possible fidelity (information) losses and which can be implemented in an algorithm placing a relatively low arithmetic load on the system are described.

Mango, Stephen A.↗

The Fault Tree Compiler (FTC): Program and mathematics

The Fault Tree Compiler Program is a new reliability tool used to predict the top-event probability for a fault tree. Five different gate types are allowed in the fault tree: AND, OR, EXCLUSIVE OR, INVERT, AND m OF n gates. The high-level input language is easy to understand and use when describing the system tree. In addition, the use of the hierarchical fault tree capability can simplify the tree description and decrease program execution time. The current solution technique provides an answer precisely (within the limits of double precision floating point arithmetic) within a user specified number of digits accuracy. The user may vary one failure rate or failure probability over a range of values and plot the results for sensitivity analyses. The solution technique is implemented in FORTRAN; the remaining program code is implemented in Pascal. The program is written to run on a Digital Equipment Corporation (DEC) VAX computer with the VMS operation system.

Butler, Ricky W.↗

Benchmarking and performance analysis of the CM-2

A suite of benchmarking routines testing communication, basic arithmetic operations, and selected kernel algorithms written in LISP and PARIS was developed for the CM-2. Experiment runs are automated via a software framework that sequences individual tests, allowing for unattended overnight operation. Multiple measurements are made and treated statistically to generate well-characterized results from the noisy values given by cm:time. The results obtained provide a comparison with similar, but less extensive, testing done on a CM-1. Tests were chosen to aid the algorithmist in constructing fast, efficient, and correct code on the CM-2, as well as gain insight into what performance criteria are needed when evaluating parallel processing machines.

Myers, David W.↗

DFT algorithms for bit-serial GaAs array processor architectures

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

Mcmillan, Gary B.↗

Exact computation of the unwrapped phase of a finite-length time series

McGowan and Kuc (1982) showed that a direct relationship between a time series and its unwrapped phase exists. They proposed an algorithm for computing the unwrapped phase by counting the number of sign changes in a Sturm sequence generated from the real and imaginary parts of the discrete Fourier transform. Their algorithm is limited to relatively short sequences by numerical accuracy. An extension of their algorithm is proposed which, by using all-integer arithmetic, permits exact computation of the number of multiples of pi required to determine the unwrapped phase for rational-valued time sequences of arbitrary length. Since the computation is exact, the extended numerical algorithm should be of interest when accurate phase unwrapping is required.

Long, David G.↗

BLITZEN - A highly integrated massively parallel machine

The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

Blevins, D. W.↗

Optical systems for digit-serial computation

High-accuracy optical systems for implementing digit-serial computations are discussed which incorporate parallelism and carry-free addition to achieve high processing speed. Employing on-line arithmetic, parallel calculations can be performed by the concurrent execution of operations. The algorithms are shown to be problem invariant and step invariant. Architectures using optical bistable devices and optical interconnects are discussed which can implement digit-serial addition, subtraction, multiplication, and division algorithms via the present approach.

Perlee, Caroline J.↗