Search NASA⌕ Search

SEARCH · Search NASA

Results for “CMOS”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Optics-Free Chip-Scale Intraoperative Imaging Using NIR-Excited Upconverting Nanoparticles

Here we present an optics-free CMOS image sensor that incorporates a novel time-gated dual-photodiode pixel design to allow filter- and lens-less image acquisition of near-infrared-excited (NIR-excited) upconverting nanoparticles. Recent biomedical advances have highlighted the benefits of NIR excitation, but NIR interaction with silicon has remained a challenge, even with high-performance optical blocking filters. Using a secondary diode and a dual-photodiode design, this sensor is able to remove the 100s of mV of NIR background on pixels and bring it down to single-digit mV level, nearing its noise floor of 2.2 mV rms, not achievable with any optical filter. Non-linear effects of background cancellation using the diode pair has been mitigated using an initial one-time pixel-level curve fitting and calibration in a post-processing setting. This imager comprises a highly linear 11 fF metal-oxide-metal (MOM) capacitor and includes integrated angle-selective gratings to reject oblique light and enhance sharpness. Each pixel also includes two distinct correlated double sampling schemes, to remove low frequency flicker noise and systematic offset in the datapath. We demonstrate the performance of this imager using pulsed NIR-excited upconverting nanoparticles on standard United-States-Air-Force (USAF) resolution targets and achieve an SNR of 15 dB, while keeping NIR background below 6 mV. This 36-by-80-pixel array measures only 2.3 mm by 4.8 mm and can be thinned down to 25 µm, allowing it to become surgically compatible with intraoperative instruments and equipment, while remaining optics-free.

42 ENGINEERING↗
DOE OSTI2023

A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC

The MIDNA application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65 nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm${^2}$ area and has an input referred noise of 2.7${\mu\nu}_{rms}$. It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Here, sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2${e^{-}}$ RMS by averaging 1000 samples with MIDNA both at room temperature and at 180 Kelvin.

1/f noise↗
DOE OSTI2024

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1 µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Amorphous Indium Oxide Channel FEFETs With Write Voltage of 0.9 V and Endurance >10 12 for Refresh-Free Embedded Memory

This work presents, for the first time, a back-end-of-the-line (BEOL)-compatible W-doped indium oxide (IWO) ferroelectric field-effect transistor (FEFET) with a record-low operating voltage below 0.9 V and a write speed of 20 ns while achieving a transient read current window (CW) ratio ( I LVT /I HVT ) greater than 10 4 . The device also exhibits exceptional reliability characteristics such as: 1) measured bipolar write endurance up to 10 12 cycles; 2) a fast read speed of 50 ns; 3) read endurance surpassing 10 12 cycles; and 4) retention exceeding 10 4 s at 85 ∘ C. Furthermore, a physics-based numerical model has been developed to investigate the nanoscale characteristics of BEOL FEFET devices, leveraging nucleation-limited switching in HfO 2 ferroelectrics and dc characterization to extract material and channel parameters for accurate device simulation. The simulation uncovers the stochastic switching behavior of BEOL amorphous oxide semiconductor (AOS) FEFETs and demonstrates an intrinsic switching time as low as 1 ps, highlighting the potential of BEOL AOS FEFETs for ultrafast memory applications. These results establish AOS FEFETs as a compelling candidate for high-density embedded memory applications for last-level cache (LLC) (L4) in advanced CMOS technology nodes.

1-V ferroelectric field-effect transistor (FEFET)↗
DOE OSTI2025

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗
DOE OSTI2026

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗
DOE OSTI2021

A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments

We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gbps (DLAS10) and three Miniature Optical Transmitter/Receiver/Transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive two Transmitter Optical Sub-Assemblies (TOSAs) of Vertical Cavity Surface Emitting Lasers (VCSELs), receive the signals from two Receiver Optical Sub-Assemblies (ROSAs) that have no embedded limiting amplifiers, or drive a VCSEL TOSA and receive the signal from a ROSA, respectively. Each channel of DLAS10 consists of an input Continuous Time Linear Equalizer (CTLE), a four-stage limiting amplifier (LA), and an output driver. The LA amplifies the signals of variable levels to a stable swing. The output driver drives VCSELs or impedance-controlled traces. DLAS10 is fabricated in a 65 nm CMOS technology. The die is 1 mm x 1 mm. DLAS10 is packaged in a 4 mm x 4 mm 24-pin quad-flat no-leads (QFN) package. DLAS10 has been tested in MTx+, MRx+, and MTRx+ modules. Both measured optical and electrical eye diagrams pass the 10 Gbps eye mask test. Furthermore, the input electrical sensitivity is 40 mVp-p, while the input optical sensitivity is -12 dBm. The total jitter of MRx+ is 29 ps (P-P) with a random jitter of 1.6 ps (RMS) and a deterministic jitter of 9.9 ps. Each MTx+/MTRx+ module consumes 82 mW/ch and 174 mW/ch, respectively.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC

Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network (NN) autoencoder model can be implemented in a radiation-tolerant application-specific integrated circuit (ASIC) to perform lossy data compression alleviating the data transmission problem while preserving critical information of the detector energy profile. For our application, we consider the high-granularity calorimeter from the Compact Muon Solenoid (CMS) experiment at the CERN Large Hadron Collider. The advantage of the machine learning approach is in the flexibility and configurability of the algorithm. By changing the NN weights, a unique data compression algorithm can be deployed for each sensor in different detector regions and changing detector or collider conditions. To meet area, performance, and power constraints, we perform quantization-aware training to create an optimized NN hardware implementation. The design is achieved through the use of high-level synthesis tools and the hls4ml framework and was processed through synthesis and physical layout flows based on a low-power (LP)-CMOS 65-nm technology node. The flow anticipates 200 Mrad of ionizing radiation to select gates and reports a total area of 3.6 mm 2 and consumes 95 mW of power. The simulated energy consumption per inference is 2.4 nJ. Furthermore, this is the first radiation-tolerant on-detector ASIC implementation of an NN that has been designed for particle physics applications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

A Hybrid Transmitter With Voltage-Mode SST Preemphasis and Current-Mode Transmitter Equalization Capable of Operating at 77 K in DUNE

The Deep Underground Neutrino Experiment (DUNE) requires that the front-end transmitters operate at cryogenic temperature and drive 25–35 m long twin-axial (twinax) cables. Here, to compensate the frequency-dependent channel loss over the long cables and alleviate the de-emphasizing of the low-frequency signal magnitude, a hybrid of a current-mode (CM) transmitter equalization (TXEQ) and a voltage-mode (VM) preemphasis is proposed. The TXEQ employs a finite-impulse response (FIR) filter to boost the high-frequency components while de-emphasizing the low-frequency signal magnitude, thereby flattening the overall channel frequency response and reducing the intersymbol interference (ISI). The VM preemphasis is proposed to further mitigate ISI by boosting the high-frequency portion without degrading the signal magnitude, allowing for high signal swing. The main driver utilizes VM source-series-terminated (SST) output stages, which offers higher signal swing and better power efficiency than the conventional CM logic (CML) drivers. To ensure the lifetime and reliability at cryogenic temperature, the transmitter is implemented in a 65-nm CMOS process operating at 1.1 V of supply voltage and employing transistors with larger than minimum lengths. Silicon measurement results at 77 K have validated the proposed approaches.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

The Effects of Threshold Voltage and Number of Fins per Transistor on the TID Response of GF 12LP Technology

This abstract presents a comprehensive analysis of total ionizing dose (TID) response in GlobalFoundries’ 12LP 12nm bulk FinFET technology using 10keV X-rays. Devices with higher threshold voltages (VTs) demonstrated lower increases in off-state leakage current (IDS,OFF) post-irradiation, highlighting the mitigating role of high VT in TID response. Our data shows that transistors with fewer fins exhibit superior TID resistance, implying lower susceptibility to radiation effects. Our study also probed two bias conditions, "Gate-On" and "Pass-Gate," with the former displaying more severe TID degradation. Interestingly, p-type devices displayed negligible degradation, underscoring their inherent resilience to TID effects. Additionally, medium thick n-type devices echoed the fin-count-dependent TID response observed in other transistor types, further strengthening our findings. These results underscore the importance of strategic transistor selection and design for enhancing the TID resilience of future CMOS FinFET architectures, particularly critical in radiation-intense environments.

42 ENGINEERING↗
DOE OSTI2024

Testing of a Line Driver With Configurable Pre-Emphasis on Lossy Transmission Lines

Rare-event physics experiments such as the Deep Underground Neutrino Experiment (DUNE) or the next Enriched Xenon Observatory (nEXO) experiment search for rare, low-energy events, detected by sensitive detectors immersed in a cryogenic noble liquid (e.g., liquid argon or xenon). Readout electronics used within such detectors must consume minimal power while operating reliably in cryogenic environments. Furthermore, in the case of nEXO, maximizing the radiopurity of the environment is vital to minimize background noise, thus placing strict limits on the volume of dielectric materials, leading to high-loss data cables spanning distances up to 12 m. Such cables cause high attenuation and intersymbol interference (ISI), resulting in a high bit-error rate (BER). These issues were addressed by developing an integrated line driver with configurable pre-emphasis in a 65-nm CMOS process. The pre-emphasis parameters can be programmed to minimize BER for specific cables and data rates under power constraints. Here, the driver was tested at both room and cryogenic temperatures. In both cases, the output BER was found to be strongly correlated with the pre-emphasis settings. Furthermore, analysis and simulation showed that adapting the pre-emphasis settings based on the incoming bit sequence can further improve performance with minimal changes to the current solution.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

X-Ray and Particle Detection With the Si(Li) Tracker Module of the GAPS Experiment

Here, this work describes the architecture and the experimental results from the characterization of the lithium-drifted silicon (Si(Li)) detector module, which constitutes the building block of the tracker in the general antiparticle spectrometer (GAPS) experiment to search for dark matter. The instrument is designed for the identification of low-energy cosmic anti-nuclei (antiprotons, antideuterons, and antihelium) to be performed during an Antarctic long-duration balloon flight scheduled for late 2025. The GAPS Si(Li) tracker, that is the core of the instrument, is the assembly of 252 modules, each comprised of four Si(Li) detectors and a full custom-integrated circuit designed for detector readout and produced in a commercial 180-nm planar CMOS technology. A general overview of the detector module architecture and its components is provided, together with a description of the test setup and the experimental results obtained from the characterization of the low-noise analog readout channel. In order to verify the effective operation of the entire module, results concerning the detection of X-rays from a 241Am source and cosmic muons are also provided.

Manghisoni, Massimo [Università di Bergamo (Italy)↗
DOE OSTI2025

Exploration of a Combined LIBS and LA-ICP-MS Approach for Apatite Characterisation

A combined laser‐induced breakdown spectroscopy (LIBS) and laser ablation‐inductively coupled plasma‐mass spectrometry (LA‐ICP‐MS) method is demonstrated for comprehensive apatite analysis. These measurements provide elemental imaging that can be used as a screening technique for chemical selection of grains for subsequent analysis (e.g., U‐Pb geochronology) or can be used to understand elemental distributions within a single grain that would have direct textural‐chemical implications (e.g., zoning patterns). Adding LIBS as a simultaneous measurement, to LA‐ICP‐MS U‐Pb geochronology, allowed for the direct determination of F (H and O show promise for future applications) in addition to major and trace elements of interest. Here, the quantitative measurements were validated against a series of apatites with known values and used to characterise a wide range of samples. Fluorine detection limits were determined to be as low as 70 μg g ‐1 F (broadband CMOS detector) and 4.2 μg g ‐1 F (ICCD detector). U‐Pb age dating was simultaneously collected by LA‐ICP‐MS with the quantitative elemental data from LIBS, providing a comprehensive method for geochronology.

Apatite↗
DOE OSTI2022

Combined thermographic phosphor and digital image correlation (TP + DIC) for simultaneous temperature and strain measurements

We report thermographic phosphors (TP) are combined with stereo digital image correlation (DIC) in a novel diagnostic, TP + DIC, to measure full-field surface strains and temperatures simultaneously. The TP + DIC method is presented, including corrections for nonlinear CMOS camera detectors and generation of pixel-wise calibration curves to relate the known temperature to the ratio of pixel intensities between two distinct wavelength bands. Additionally, DIC is employed not only for strain measurements but also for accurate image registration between the two cameras for the two-colour ratio method approach of phosphoric thermography. TP + DIC is applied to characterize the thermo-mechanical response of 304L stainless steel dog bones during tensile testing at different strain rates. The dog bones are patterned for DIC with Mg 3 F 2 GeO 4 :Mn (MFG) via aerosol deposition through a shadow mask. Temperatures up to 425°K (150°C) and strains up to 1.0 mm/mm are measured in the localized necking region, with conservative noise levels of 10°K and 0.01 mm/mm or less. Finally, TP + DIC is compared to the more established method of combining infrared (IR) thermography with DIC (IR + DIC), with results agreeing favourably. Three topics of continued research are identified, including cracking of the aerosol-deposited phosphor DIC features, incomplete illumination for pixels on the border of the phosphor features, and phosphor emission evolution as a function of applied substrate strain. This work demonstrates the combination of phosphor thermography and DIC and lays the foundation for further development of TP + DIC for testing in combined thermo-mechancial environments.

304L stainless steel↗
DOE OSTI2022

An Experimental Investigation of Supercritical Methane Injection Characteristics in a CO2 Environment

Abstract Clean energy generation is gaining significant attention from industries, academia, and governments across the globe. The Allam cycle is one such technology that has been under focus due to its efficiency, environmental friendliness, and economics. This is a direct-fired cycle operating at supercritical conditions using carbon dioxide as a working fluid. Fuel or oxidizer jet mixing with CO2 is a vital phenomenon that governs combustion efficiency, and it is not well understood for the Allam cycle conditions. This paper experimentally investigated the jet characteristics of a methane jet injected into a subcritical to supercritical carbon dioxide environment. A wide range of injection pressures and temperatures were targeted between subcritical to supercritical conditions. Unlike previous studies, the current work focused on injecting lower-density (methane) jets into higher-density (carbon dioxide) environments. Schlieren imaging and methane absorption measurements were simultaneously performed with a CMOS high-speed camera and a 3.39 μm infrared laser. Specifically, we looked at the classical injection parameter of jet spreading angle, which was classically established to be mainly a density ratio function. Here, the jet cone angle was obtained from the postprocessed schlieren imaging. The jet cone angle is a critical characteristic parameter that describes the entrainment rate in a jet; thus, it is a crucial parameter in understanding the nature of the jet. The laser measurements were only used as an additional check to confirm the entry time of methane into the chamber filled with carbon dioxide. Notably, this paper makes a detailed comparison between the jet cone angles of jets with a density ratio. The result showed that the classical correlations, such as Abramovich's theory applied to submerged turbulent gas jets developed for low-density ratio jets, were unsuitable for higher-density ratio jets. It was also observed that the divergence angles were dependent not only on density ratio but also on other parameters such as pressure ratios and reduced pressures.

Engineering↗
DOE OSTI2024

Future of plasma etching for microelectronics: Challenges and opportunities

Plasma etching is an essential semiconductor manufacturing technology required to enable the current microelectronics industry. Along with lithographic patterning, thin-film formation methods, and others, plasma etching has dynamically evolved to meet the exponentially growing demands of the microelectronics industry that enables modern society. At this time, plasma etching faces a period of unprecedented changes owing to numerous factors, including aggressive transition to three-dimensional (3D) device architectures, process precision approaching atomic-scale critical dimensions, introduction of new materials, fundamental silicon device limits, and parallel evolution of post-CMOS approaches. The vast growth of the microelectronics industry has emphasized its role in addressing major societal challenges, including questions on the sustainability of the associated energy use, semiconductor manufacturing related emissions of greenhouse gases, and others. The goal of this article is to help both define the challenges for plasma etching and point out effective plasma etching technology options that may play essential roles in defining microelectronics manufacturing in the future. The challenges are accompanied by significant new opportunities, including integrating experiments with various computational approaches such as machine learning/artificial intelligence and progress in computational approaches, including the realization of digital twins of physical etch chambers through hybrid/coupled models. These prospects can enable innovative solutions to problems that were not available during the past 50 years of plasma etch development in the microelectronics industry. To elaborate on these perspectives, the present article brings together the views of various experts on the different topics that will shape plasma etching for microelectronics manufacturing of the future.

Engineering↗
DOE OSTI2022

NIR fluorescence lifetime macroscopic imaging with a time-gated SPAD camera

The performance of SwissSPAD2 (SS2), a large scale, widefield time-gated CMOS SPAD imager developed for fluorescence lifetime imaging, has recently been described in the context of visible range and fluorescence lifetime imaging microscopy (FLIM) of dyes with lifetimes in the 2.5 – 4 ns range. Here, we explore its capabilities in the NIR regime relevant for small animal imaging, where its sensitivity is lower and typical NIR fluorescent dye lifetimes are much shorter (1 ns or less). We carry out this study in a simple macroscopic imaging setup based on a compact NIR picosecond pulsed laser, an engineered diffuser-based illumination optics, and NIR optimized imaging lens suitable for well-plate or small animal imaging. Because laser repetition rates can vary between models, but the synchronization signal frequency accepted by SS2 is fixed to 20 MHz, we first checked that a simple frequency-division scheme enables data recording for different laser repetition rates. Next, we acquired data using different time gate widths, including gates with duration longer than the laser period, and analyzed the resulting data using both standard nonlinear least-square fit (NLSF) and phasor analysis. We show that the fixed synchronization rate and large gate widths characterizing SS2 (10 ns and over) are not an obstacle to accurately extracting lifetime in the 1 ns range and to distinguishing between close lifetimes. As a result, SS2 and similar very large gated SPAD imagers appear as a versatile alternative to other widefield time-resolved detectors for NIR fluorescence lifetime imaging, including preclinical molecular applications.

FLIM↗
DOE OSTI2020

Electrical power generation from moderate-temperature radiative thermal sources

Moderate-temperature thermal sources (100° to 400°C) which radiate waste heat are often the by-product of mechanical work, chemical or nuclear reactions, or information processing. We demonstrate conversion of thermal radiation into electrical power using a bipolar grating-coupled complementary metal-oxide-silicon (CMOS) tunnel diode. A two-step photon-assisted tunneling charge pumping mechanism results in separation of charge carriers in pn-junction wells leading to a large open-circuit voltage developed across a load. Electrical power generation from a broadband blackbody thermal source has been experimentally demonstrated with converted power densities of 27 to 61 microwatts per square centimeter for thermal sources between 250° and 400°C. Scalable, efficient conversion of radiated waste heat into electrical power can be used to reduce energy consumption or to power electronics and sensors.

30 DIRECT ENERGY CONVERSION↗