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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
NASA NTRS1974

Process development of beam-lead silicon-gate COS/MOS integrated circuits

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Baptiste, B.↗
DOE OSTI2025

Logical error rates for the surface code under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions

With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance 𝑑 = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at 𝑑 = 3−5, we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.

Quantum benchmarking↗
NASA NTRS1970

Ground computer test trap

Test trap consists of logic nest of five printed circuit boards, plus power supply within the unit. Device monitors more than one logic area simultaneously, gives visual display of detected error, operates at computer speed, maintains readily available logic description of cards used, and is compatible with existing computer circuitry.

Fondrie, D. G.↗
NASA NTRS1993

Experiments on technology mapping using different cell libraries

Technology mapping is one of the major steps in the synthesis process of integrated circuits. Efficient algorithms have been proposed in the recent past to optimize the number of cells required to implement a given design, but not enough effort has been spent in studying the relationship between the quality of the circuit produced by the logic synthesis tool and the cell library used to perform the mapping. In this paper we present experiments on technology mapping that show how the design of the cell library can influence the area and the delay of the synthesized circuit.

Macii, Enrico↗
NASA NTRS1992

HDL to verification logic translator

The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.

Gambles, J. W.↗
NASA NTRS1968

Counter and shift register Patent

Computer circuit performing both counting and shifting logic operations also capable of miniaturization and integration in basic circuits

Smith, C.↗
NASA NTRS1976

Banning standard cell engineering notebook

A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The information is presented in a form useful for systems designs, logic design, and the preparation of inputs to both sets of Design Automation programs for array design and analysis. A data sheet is provided for each cell and gives the cell name, the cell number, its logic symbol, Boolean equation, truth table, circuit schematic circuit composite, input-output capacitances, and revision date. The circuit type file, also given for each cell, together with the logic drawing contained on the data sheet provides all the information required to prepare input data files for the Design Automation Systems. A detailed description of the electrical design procedure is included.

Source record↗
NASA NTRS1973

Logic controlled solid state switchgear

Logic controlled solid state circuit breakers and power transfer switches have been designed and built to demonstrate their use for 270 V dc power systems. This switchgear provides remote operation, automatic current level, and operates several orders of magnitude faster with much greater accuracy of response than conventional switchgear.

Buchanan, E.↗
NASA NTRS1984

Status Panel For Video Cassette Recorders

Central array of light-emitting diodes displays status of 30 video cassette recorders (VCR's) monitoring integrated testing of Space Shuttle. Remote status panel linked to VCR's by one 37-conductor cable. Transistor/ transistor logic chips in interface circuit allow LED array to function without drawing power from VCR control circuits.

Talley, G. L., Jr.↗
NASA NTRS1994

Integrated-Circuit Controller For Brushless dc Motor

Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

Le, Dong Tuan↗
NASA NTRS2001

Fundamentals of Digital Engineering: Designing for Reliability

The concept of designing for reliability will be introduced along with a brief overview of reliability, redundancy and traditional methods of fault tolerance is presented, as applied to current logic devices. The fundamentals of advanced circuit design and analysis techniques will be the primary focus. The introduction will cover the definitions of key device parameters and how analysis is used to prove circuit correctness. Basic design techniques such as synchronous vs asynchronous design, metastable state resolution time/arbiter design, and finite state machine structure/implementation will be reviewed. Advanced topics will be explored such as skew-tolerant circuit design, the use of triple-modular redundancy and circuit hazards, device transients and preventative circuit design, lock-up states in finite state machines generated by logic synthesizers, device transient characteristics, radiation mitigation techniques. worst-case analysis, the use of timing analyzer and simulators, and others. Case studies and lessons learned from spaceflight designs will be given as examples

Katz, R.↗
NASA NTRS1979

EKG and ultrasonoscope display

A system is disclosed which permits simultaneous display of an EKG waveform in real time in conjunction with a two-dimensional cross-sectional image of the heart, so that the EKG waveform can be directly compared with dimensional changes in the heart. The apparatus of the invention includes an ultrasonoscope for producing a C-scan cross-sectional image of the heart. An EKG monitor circuit along with EKG logic circuitry is combined with the ultrasonoscope circuitry to produce on the same oscilloscope screen a continuous vertical trace showing the EKG waveform simultaneously with the heart image. The logic circuitry controls the oscilloscope display such that the display of both heart and EKG waveforms occurs on a real time basis.

Lee, Robert D.↗
NASA NTRS2006

NASA Tech Briefs, March 2006

Topics covered include: Medical Signal-Conditioning and Data-Interface System; Instruments for Reading Direct-Marked Data-Matrix Symbols; Processing EOS MLS Level-2 Data; Ground Processing of Data From the Mars Exploration Rovers; Estimating Total Electron Content Using 1,000+ GPS Receivers; NASA Solar Array Demonstrates Commercial Potential; Improved Control of Charging Voltage for Li-Ion Battery; Programmable Pulse-Position-Modulation Encoder; Wavelength-Agile External-Cavity Diode Laser for DWDM; Pattern-Recognition Processor Using Holographic Photopolymer; Submicrosecond Power-Switching Test Circuit; Three-Function Logic Gate Controlled by Analog Voltage; Integrated System for Autonomous Science; Montage Version 3.0; Utilizing AI in Temporal, Spatial, and Resource Scheduling; Satellite Image Mosaic Engine; Architecture for Control of the K9 Rover; HFGMC Enhancement of MAC/GMC; Automated Activation and Deactivation of a System Under Test; Cleaning Carbon Nanotubes by Use of Mild Oxygen Plasmas; Generating Aromatics From CO2 on Mars or Natural Gas on Earth; Attaching Thermocouples by Peening or Crimping; Heat Treatment of Friction-Stir-Welded 7050 Aluminum Plates; Generating Breathable Air Through Dissociation of N2O; High-Performance Scanning Acousto-Ultrasonic System; Correction for Thermal EMFs in Thermocouple Feedthroughs; Using Quasiparticle Poisoning To Detect Photons; Estimating Resolution Lengths of Hybrid Turbulence Models; Education and Training Module in Alertness Management; Cargo-Positioning System for Next-Generation Spacecraft; Micro-Imagers for Spaceborne Cell-Growth Experiments; Holographic Solar Photon Thrusters; Plasma-Based Detector of Outer-Space Dust Particles; and Generation of Data-Rate Profiles of Ka-Band Deep-Space Links.

Source record↗
NASA NTRS2003

Improved Autoassociative Neural Networks

Improved autoassociative neural networks, denoted nexi, have been proposed for use in controlling autonomous robots, including mobile exploratory robots of the biomorphic type. In comparison with conventional autoassociative neural networks, nexi would be more complex but more capable in that they could be trained to do more complex tasks. A nexus would use bit weights and simple arithmetic in a manner that would enable training and operation without a central processing unit, programs, weight registers, or large amounts of memory. Only a relatively small amount of memory (to hold the bit weights) and a simple logic application- specific integrated circuit would be needed. A description of autoassociative neural networks is prerequisite to a meaningful description of a nexus. An autoassociative network is a set of neurons that are completely connected in the sense that each neuron receives input from, and sends output to, all the other neurons. (In some instantiations, a neuron could also send output back to its own input terminal.) The state of a neuron is completely determined by the inner product of its inputs with weights associated with its input channel. Setting the weights sets the behavior of the network. The neurons of an autoassociative network are usually regarded as comprising a row or vector. Time is a quantized phenomenon for most autoassociative networks in the sense that time proceeds in discrete steps. At each time step, the row of neurons forms a pattern: some neurons are firing, some are not. Hence, the current state of an autoassociative network can be described with a single binary vector. As time goes by, the network changes the vector. Autoassociative networks move vectors over hyperspace landscapes of possibilities.

Hand, Charles↗
NASA NTRS1990

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Taylor, B.↗