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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Although not yet approved, space-station development looms as a logical follow-on to present manned spaceflight programs. This discussion considers the implications of missions, objectives, design configurations, logistics, and operations.
The capabilities of the Marshall system for aerospace system simulation (MARSYAS) and how to use it are described. MARSYAS is a software system that allows easy setup and control of the simulation of the dynamics of large physical systems on a digital computer. The physical systems are modeled in the form of block diagrams or equations. The blocks can have multiple inputs and multiple outputs, and they can be nested to form hierarchies. The block diagrams can contain transfer functions, nonlinear and logical functions, equations, analog computer elements and FORTRAN programs. The input format of the equations can be combinations of nonlinear, time-varying differential equations and algebraic equations in their original format. MARSYAS could also serve as a storage and retrieval system for models as a basis for a model configuration control system on a central time-shared computer. The outputs of the simulation system can be not only time-responses but also other analysis data such as frequency response, power spectrum and stability parameters. The MARSYAS translator is written in FORTRAN running on the Univac 1108 computer under the EXEC 8 operating system.
A research program was conducted to further the professional knowledge of qualified engineering and science faculty members, to stimulate an exchange of ideas between participants and NASA engineers and scientists, and to enrich the research activities of the participants' institutions. Abstracts of reports submitted at the end of the program are presented. Topics investigated include multispectral photography, logic circuits, gravitation theories, information systems, fracture mechanics, holographic interferometry, surface acoustic wave technology, ion beams in the upper atmosphere, and hybrid microcircuits.
The set of flight control logic used in a recently completed flight test program to evaluate the total automatic flight control system (TAFCOS) with the controller operating in a fully automatic mode, was used to perform an unmanned simulation on an IBM 360 computer in which the TAFCOS concept was extended to provide a multilevel pilot interface. A pilot TAFCOS interface for direct pilot control by use of a velocity-control-wheel-steering mode was defined as well as a means for calling up conventional autopilot modes. It is concluded that the TAFCOS structure is easily adaptable to the addition of a pilot control through a stick-wheel-throttle control similar to conventional airplane controls. Conventional autopilot modes, such as airspeed-hold, altitude-hold, heading-hold, and flight path angle-hold, can also be included.
A programmable controller (PC) system automatic sequence control, which acts as a supervisory controller for the servos, selects the proper drives, and automatically sequences the vanes, was developed for use in a subsonic wind tunnel. Tunnel modifications include a new second test section (80 ft x 100 ft with a maximum air speed capability of 110 knots) and an increase in maximum velocity flow from 200 knots to 300 knots. A completely automatic sequence control is necessary in order to allow intricate motion of the 14 triangularly arranged vanes which can be as large as 70 ft high x 35 ft wide and which require precise acceleration and deceleration control. Rate servos on each drive aid in this control, and servo cost was minimized by using four silicon controlled rectifier controllers to control the 20 dc drives. The PC has a programming capacity which facilitated the implementation of extensive logic design. A series of diagrams sequencing the vanes and a block diagram of the system are included.
The critical steps needed to develop a gravity gradiometer instrument and a conceptual design for a Gravity Gradiometer Mission (GGM) are defined and organized into a logical sequence. Funding requirements for an advanced development program beginning in FY-1985 are estimated.
An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This technique utilizes linear algebra to produce the design equations. The ILA realization of synchronous sequential logic can be fully automated with a computer program. A programmable design procedure is proposed to fullfill the design task and layout generation. A software algorithm in the C language has been developed and tested to generate 1 micron CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.
This work presents our runtime verification approach implemented by the tool MESA (MEssage-based System Analysis) which allows for using concurrent monitors to check for properties specified in linear temporal logic and finite state machines.We employ the actor programing model to implement MESA where monitors are captured by concurrent actors that communicate via messaging. The paper also presents a case study where MESA is used to monitor flights in National Airspace System of United States using live air traffic data stream. The case study which motivated this work in the first place shows that our approach is effective.We also perform empirical study by conducting experiments using monitoring systems with different numbers of concurrent monitors and different layers of indexing.This paper describes our experiments, evaluates our results,and discusses challenges faced during the study. The evaluation shows our approach is scalable.
This is a three-paper dissertation that responds to a call for empirical research on stakeholder influence in the implementation of evaluation recommendations. The literature is consistent but mostly theoretical: stakeholder participation should positively influence and increase the probability of implementation (see e.g., Christie, 2011; Cousins and Earl, 1992); Fetterman, 2004). In response, I use two Goddard Space Flight Center engineering technical training and development programs to build a causal pathway argument supporting my proposition that stakeholder influence in the logic modeling process impacts organizational decision-making and change. I first introduce the logic modeling process as a tool to involve stakeholders in program and evaluation design (paper 1), then use the data collection process to implement the collaboratively constructed logic model outcomes (paper 2), and finally, I triangulate the data using the Toal (2009) Evaluation Involvement Scale (paper 3). I do this to “increase the validity of the findings” (Noble & Heale, 2019, p. 67) and to garner potential mechanisms. I found that stakeholder participation in the logic modeling process positively influenced the use of data to inform recommendations which in turn positively influenced implementation of evaluation recommendations. I identified the process itself as the mechanism and the key decision points as links or influencers. Potential factors included power and interest (measured by role) and time-on-job.
A brief general description of the ASTP flight program verification was presented. The total program verification effort assures the accuracy and adequacy of the LVDC flight program and verifies that the final program meets mission requirements and conforms to program documentation. The flight program's functional requirements to integrate the guidance and control system with the launch vehicle sequencing system are verified directly by analysis of many special logic checks designed for this purpose and indirectly by the correct overall program response to nominal and numerous perturbed conditions. Verification of the interaction of function requirements is accomplished on every case run during the verification effort.
A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.
A family of standardized thick-oxide P-MOS building blocks (standard cells) is described. The information is presented in a form useful for systems designs, logic design, and the preparation of inputs to both sets of Design Automation programs for array design and analysis. A data sheet is provided for each cell and gives the cell name, the cell number, its logic symbol, Boolean equation, truth table, circuit schematic circuit composite, input-output capacitances, and revision date. The circuit type file, also given for each cell, together with the logic drawing contained on the data sheet provides all the information required to prepare input data files for the Design Automation Systems. A detailed description of the electrical design procedure is included.
Just prior to its being EFM modulated (i.e., converted to eight-to-fourteen channel data by the EFM encoder) and written to a Compact Disc (CD), information that passes through the CIRC Block Encoder is grouped into 33-byte blocks referred to as EFM frames. Twenty four of the bytes that make up a given EFM frame are user data that was input into the CIRC encoder at various (different) times, 4 of the bytes of this same EFM frame were created by the C2 ECC encoder (each at a different time), and another 4 were created by the C1 ECC encoder (again, each at a different time). The one remaining byte of the given EFM frame, which is known as the EFM frame C&D (for Control & Display) byte, carries information that identifies which portion of the current disc program track the given EFM frame belongs to and also specifies the location of the given EFM frame on the disc (in terms of a time stamp that has a resolution of l/75th second, or 98 EFM frames). (Note: since the program track and time information is stored as a 98-byte word, a logical group consisting of 98 consecutive EFM frames must be read, and their respective C&D bytes must be catenated and decoded, before the program track identification and time position information that pertains to the entire block of 98 EFM frames can be obtained.) The C&D byte is put at the start (0th byte) of an EFM frame in real time; its placement completes the construction of the EFM frame - it is assigned just before the EFM frame enters the EFM encoder. Four distinct blocks of data are referred to: 24-byte User Input Data Blocks; 28-byte C2 words; 32-byte C1 words; and 33-byte EFM frames.
The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.
We present a rewriting algorithm for efficiently testing future time Linear Temporal Logic (LTL) formulae on finite execution traces, The standard models of LTL are infinite traces, reflecting the behavior of reactive and concurrent systems which conceptually may be continuously alive in most past applications of LTL, theorem provers and model checkers have been used to formally prove that down-scaled models satisfy such LTL specifications. Our goal is instead to use LTL for up-scaled testing of real software applications, corresponding to analyzing the conformance of finite traces against LTL formulae. We first describe what it means for a finite trace to satisfy an LTL property end then suggest an optimized algorithm based on transforming LTL formulae. We use the Maude rewriting logic, which turns out to be a good notation and being supported by an efficient rewriting engine for performing these experiments. The work constitutes part of the Java PathExplorer (JPAX) project, the purpose of which is to develop a flexible tool for monitoring Java program executions.
Materials selection for spacecraft is based on an upward flammability test conducted in a quiescent environment in the highest expected oxygen concentration environment. The test conditions and its pass/fail test logic do not provide sufficient quantitative materials flammability information for an advanced space exploration program. A modified approach has been suggested determination of materials self-extinguishment limits. The flammability threshold information will allow NASA to identify materials with increased flammability risk from oxygen concentration and total pressure changes, minimize potential impacts, and allow for development of sound requirements for new spacecraft and extraterrestrial landers and habitats. This paper provides data on oxygen concentration self-extinguishment limits under quiescent conditions for selected materials considered for the Constellation Program.
Programmatic opportunities abound for space Cables, Stringers and Tethers, justified by the tremendous performance advantages that these technologies offer and the rather wide gaps that must be filled by the NASA Exploration program, if the "sustainability goal" is to be met. A definition and characterization of the three categories are presented along with examples. A logical review of exploration requirements shows how each class can be infused throughout the program, from small experimental efforts to large system deployments. The economics of tethers in transportation is considered along with the impact of stringers for structural members. There is an array of synergistic methodologies that interlace their fabrication, implementation and operations. Cables, stringers and tethers can enhance a wide range of other space systems and technologies, including power storage, formation flying, instrumentation, docking mechanisms and long-life space components. The existing tether (i.e., MXER) program's accomplishments are considered consistent with NASA's new vision and can readily conform to requirements-driven technology development.
Runtime Verification (rv) is aimed at analyzing individual execution traces and temporal behaviors observed from running programs and systems. Its traditional purpose is in detecting the lack of conformance with respect to a formal specification. While very early rv systems were based on specifications given in some form of propositional temporal logic, recent efforts have focused on monitoring so-called parametric specifications over events that carry data. Since a monitor for such specifications has to store observed data, the challenge is to have an efficient representation and manipulation of data. The fundamental problem is that the actual values of the data are not necessarily bounded or provided in advance. In this paper, we describe our monitoring tool, DejaVu, which implements our algorithm [HPU17] for monitoring first-order past linear-time temporal logic over a sequence of events that carry data. We propose the use of Binary Decision Diagrams (bdds) [Bry86] for representing and manipulating sets of observed data since (1) bdds provide highly compact representations, (2) operations over bdds, in particular complementation, are very efficient, and (3) the monitor construction for the propositional case shown in [HR02] naturally extends to bdds. Our experiments show a substantial improvement in performance compared to a related tool.